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SoC DFT Verification Engineer (M, F, D)

Apple

Engineering Jobs

SoC DFT Verification Engineer (M, F, D)

full-timePosted: Oct 6, 2025

Job Description

Imagine yourself at the center of our SoC DV effort, where we are collaborating with all fields, playing a meaningful role of getting functional products to millions of customers quickly. Bring passion and dedication to your job, and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norms here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. As the SoC DFT Verification Engineer, you will be part of a team that is responsible for the complete DFT pre-silicon verification and support for the silicon bring-up of our SoC. You will build and maintain verification test bench components and environments, need to be proficient with scripting and Verilog, able to come up with test plans and validate IP, as well as ability to lead project execution. Join us! And help deliver the next excellent Apple product! Reviewing Architecture and Design Specifications. Developing attributes and verification plans. Implementing test benches, generating directed/constrained random tests. Running test simulations, debugging failures, tracking bugs, and closing coverage. Handling schedules and supporting multi-functional engineering efforts. Assisting in verification flows, automation scripts, and regressions. Working with test engineers to bring up test patterns on silicon.

Locations

  • Munich, Bavaria-Bayern, Germany 80335

Salary

Estimated Salary Rangemedium confidence

25,000,000 - 60,000,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • proficiency with scriptingintermediate
  • proficiency with Verilogintermediate
  • developing verification plansintermediate
  • implementing test benchesintermediate
  • generating directed/constrained random testsintermediate
  • running test simulationsintermediate
  • debugging failuresintermediate
  • tracking bugsintermediate
  • closing coverageintermediate
  • handling schedulesintermediate
  • supporting multi-functional engineering effortsintermediate
  • assisting in verification flowsintermediate
  • automation scriptsintermediate
  • regressionsintermediate
  • working with test engineersintermediate
  • bringing up test patterns on siliconintermediate
  • reviewing architecture and design specificationsintermediate
  • validating IPintermediate
  • leading project executionintermediate
  • coming up with test plansintermediate

Required Qualifications

  • B.Sc / M.Sc in Electrical or Computer Engineering. (experience)
  • Shown understanding and experience in directed or random verification, coverage analysis, and assertions. (experience)
  • Good knowledge of general logic design principles. (experience)
  • Ability to fluently speak and write in English. (experience)

Preferred Qualifications

  • Proficient in a scripting language such as Python, TCL, or Perl. (experience)
  • Excellent skills in problem-solving, communication. (experience)
  • Exposure to OOP programming using HDLs/HVLs such at System Verilog or C/C++. (experience)
  • Exposure to any aspect of DFT is a plus. (experience)
  • Experience in large SoC design or verification - would be a plus. (experience)

Responsibilities

  • Reviewing Architecture and Design Specifications.
  • Developing attributes and verification plans.
  • Implementing test benches, generating directed/constrained random tests.
  • Running test simulations, debugging failures, tracking bugs, and closing coverage.
  • Handling schedules and supporting multi-functional engineering efforts.
  • Assisting in verification flows, automation scripts, and regressions.
  • Working with test engineers to bring up test patterns on silicon.

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Apple logo

SoC DFT Verification Engineer (M, F, D)

Apple

Engineering Jobs

SoC DFT Verification Engineer (M, F, D)

full-timePosted: Oct 6, 2025

Job Description

Imagine yourself at the center of our SoC DV effort, where we are collaborating with all fields, playing a meaningful role of getting functional products to millions of customers quickly. Bring passion and dedication to your job, and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norms here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. As the SoC DFT Verification Engineer, you will be part of a team that is responsible for the complete DFT pre-silicon verification and support for the silicon bring-up of our SoC. You will build and maintain verification test bench components and environments, need to be proficient with scripting and Verilog, able to come up with test plans and validate IP, as well as ability to lead project execution. Join us! And help deliver the next excellent Apple product! Reviewing Architecture and Design Specifications. Developing attributes and verification plans. Implementing test benches, generating directed/constrained random tests. Running test simulations, debugging failures, tracking bugs, and closing coverage. Handling schedules and supporting multi-functional engineering efforts. Assisting in verification flows, automation scripts, and regressions. Working with test engineers to bring up test patterns on silicon.

Locations

  • Munich, Bavaria-Bayern, Germany 80335

Salary

Estimated Salary Rangemedium confidence

25,000,000 - 60,000,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • proficiency with scriptingintermediate
  • proficiency with Verilogintermediate
  • developing verification plansintermediate
  • implementing test benchesintermediate
  • generating directed/constrained random testsintermediate
  • running test simulationsintermediate
  • debugging failuresintermediate
  • tracking bugsintermediate
  • closing coverageintermediate
  • handling schedulesintermediate
  • supporting multi-functional engineering effortsintermediate
  • assisting in verification flowsintermediate
  • automation scriptsintermediate
  • regressionsintermediate
  • working with test engineersintermediate
  • bringing up test patterns on siliconintermediate
  • reviewing architecture and design specificationsintermediate
  • validating IPintermediate
  • leading project executionintermediate
  • coming up with test plansintermediate

Required Qualifications

  • B.Sc / M.Sc in Electrical or Computer Engineering. (experience)
  • Shown understanding and experience in directed or random verification, coverage analysis, and assertions. (experience)
  • Good knowledge of general logic design principles. (experience)
  • Ability to fluently speak and write in English. (experience)

Preferred Qualifications

  • Proficient in a scripting language such as Python, TCL, or Perl. (experience)
  • Excellent skills in problem-solving, communication. (experience)
  • Exposure to OOP programming using HDLs/HVLs such at System Verilog or C/C++. (experience)
  • Exposure to any aspect of DFT is a plus. (experience)
  • Experience in large SoC design or verification - would be a plus. (experience)

Responsibilities

  • Reviewing Architecture and Design Specifications.
  • Developing attributes and verification plans.
  • Implementing test benches, generating directed/constrained random tests.
  • Running test simulations, debugging failures, tracking bugs, and closing coverage.
  • Handling schedules and supporting multi-functional engineering efforts.
  • Assisting in verification flows, automation scripts, and regressions.
  • Working with test engineers to bring up test patterns on silicon.

Target Your Resume for "SoC DFT Verification Engineer (M, F, D)" , Apple

Get personalized recommendations to optimize your resume specifically for SoC DFT Verification Engineer (M, F, D). Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "SoC DFT Verification Engineer (M, F, D)" , Apple

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Tags & Categories

Hardware

Answer 10 quick questions to check your fit for SoC DFT Verification Engineer (M, F, D) @ Apple.

Quiz Challenge
10 Questions
~2 Minutes
Instant Score

Related Books and Jobs

No related jobs found at the moment.