SoC DRAM Memory Subsystem Validation Engineering Program Manager
Apple
SoC DRAM Memory Subsystem Validation Engineering Program Manager
Job Description
Come and join the team that crafts Apple's groundbreaking silicon. Apple makes the greatest SoCs in the world; to do that takes thousands of employees, multiple years, and very significant R&D spending. To make the best use of those employees, time and money requires excellent methodologies and structures. As we continue to expand and mature, the processes used to develop these SOCs must be improved. Join us to do your life’s best work in this rare opportunity to help define the next big thing that will surprise and delight the world! The SoC DRAM Memory Subsystem Validation and Debug Program Manager will drive the memory subsystem readiness for our custom SoCs. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. The charter will include managing bring-up, validation, and the complicated debug of our groundbreaking memory subsystem. The EPM will also help craft the DRAM industry’s mobile roadmap and drive innovative DRAM technologies to accompany SoC’s across Apple’s product lines. In this multifaceted role, you will be the critical interface between Apple’s DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams to ensure these sophisticated memory technologies are delivered from architecture to mass production to Apple’s industry leading quality standards.
Locations
- Austin, Texas, United States 78727
- Cupertino, California, United States 95014
- San Diego, California, United States 92128
Salary
Estimated Salary Rangemedium confidence
40,000,000 - 80,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- SoC DRAM Memory Subsystem Validationintermediate
- Debug Program Managementintermediate
- bring-up managementintermediate
- validation managementintermediate
- debug managementintermediate
- DRAM industry roadmap craftingintermediate
- innovative DRAM technologies drivingintermediate
- DRAM architecture interfacingintermediate
- Memory Controller Design interfacingintermediate
- DV interfacingintermediate
- DDR PHY interfacingintermediate
- DRAM product engineering interfacingintermediate
- software teams interfacingintermediate
- memory technologies deliveryintermediate
- architecture to mass production managementintermediate
- quality standards ensuringintermediate
Required Qualifications
- BS + 10 years of relevant experience (experience, 10 years)
- Prior experience in SOC DRAM Memory Design, Validation, Architecture or Test/Product Engineering. (experience)
Preferred Qualifications
- Knowledge of high-performance memory subsystem, including SoC memory architecture, sophisticated DDR controller, PHY design and high-speed IO interface, DRAM device, and associated calibration/training mechanisms. (experience)
- Experience shipping high volume DRAMs / SoCs. (experience)
- Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus. (experience)
- Experience working in a high-energy multi-disciplined engineering environment, strong at multi-tasking, and real-time crisis management. (experience)
- Excellent debugging skills. Proven track record to drive resolution of critical problems, while under pressure. (experience)
- Ability to understand complex technical discussions and extract action plans. (experience)
- Passionate to own/drive project development using well-defined metrics. (experience)
- Thrives in dynamic schedule driven development environment. (experience)
- Ability to succinctly summarize complex details for executive reporting. (experience)
- Extraordinary leadership skills and ability to encourage team members with a dedication to see the bigger picture (experience)
- Phenomenal leadership and social skills with a reciprocal approach. (experience)
Responsibilities
- The SoC DRAM Memory Subsystem Validation and Debug Program Manager will drive the memory subsystem readiness for our custom SoCs. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. The charter will include managing bring-up, validation, and the complicated debug of our groundbreaking memory subsystem. The EPM will also help craft the DRAM industry’s mobile roadmap and drive innovative DRAM technologies to accompany SoC’s across Apple’s product lines. In this multifaceted role, you will be the critical interface between Apple’s DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams to ensure these sophisticated memory technologies are delivered from architecture to mass production to Apple’s industry leading quality standards.
- Interface and drive memory related silicon issues across multi-functional teams: Design, Verification, Silicon Validation, Productization, System Hardware, and Software.
- Drive debug activities in post silicon environments, root-cause problems and steer the team to the best corrective action to move forward.
- Plan and lead adoption of DRAM technologies, custom package development and qualification process with multi-functional teams.
- Work closely with the DRAM Global Supply Management (GSM), DRAM & Package Engineering and SoC Program Management organizations to set priorities.
- Attend and drive technical sessions with DRAM vendors on new DRAM technology development to track and follow-up issues/action items and drive vendors to meet spec and schedule requirements.
- Work with DRAM GSM and silicon material management teams to plan and track distribution of new DRAM material across all systems in development.
- Enable tight collaboration between Design for Test (DFT), Product/Test/QA engineering, SiVal and Systems teams during NPI to finalize SoC performance targets and screen requirements.
- Drive internal program process to guarantee high quality silicon execution.
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SoC DRAM Memory Subsystem Validation Engineering Program Manager
Apple
SoC DRAM Memory Subsystem Validation Engineering Program Manager
Job Description
Come and join the team that crafts Apple's groundbreaking silicon. Apple makes the greatest SoCs in the world; to do that takes thousands of employees, multiple years, and very significant R&D spending. To make the best use of those employees, time and money requires excellent methodologies and structures. As we continue to expand and mature, the processes used to develop these SOCs must be improved. Join us to do your life’s best work in this rare opportunity to help define the next big thing that will surprise and delight the world! The SoC DRAM Memory Subsystem Validation and Debug Program Manager will drive the memory subsystem readiness for our custom SoCs. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. The charter will include managing bring-up, validation, and the complicated debug of our groundbreaking memory subsystem. The EPM will also help craft the DRAM industry’s mobile roadmap and drive innovative DRAM technologies to accompany SoC’s across Apple’s product lines. In this multifaceted role, you will be the critical interface between Apple’s DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams to ensure these sophisticated memory technologies are delivered from architecture to mass production to Apple’s industry leading quality standards.
Locations
- Austin, Texas, United States 78727
- Cupertino, California, United States 95014
- San Diego, California, United States 92128
Salary
Estimated Salary Rangemedium confidence
40,000,000 - 80,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- SoC DRAM Memory Subsystem Validationintermediate
- Debug Program Managementintermediate
- bring-up managementintermediate
- validation managementintermediate
- debug managementintermediate
- DRAM industry roadmap craftingintermediate
- innovative DRAM technologies drivingintermediate
- DRAM architecture interfacingintermediate
- Memory Controller Design interfacingintermediate
- DV interfacingintermediate
- DDR PHY interfacingintermediate
- DRAM product engineering interfacingintermediate
- software teams interfacingintermediate
- memory technologies deliveryintermediate
- architecture to mass production managementintermediate
- quality standards ensuringintermediate
Required Qualifications
- BS + 10 years of relevant experience (experience, 10 years)
- Prior experience in SOC DRAM Memory Design, Validation, Architecture or Test/Product Engineering. (experience)
Preferred Qualifications
- Knowledge of high-performance memory subsystem, including SoC memory architecture, sophisticated DDR controller, PHY design and high-speed IO interface, DRAM device, and associated calibration/training mechanisms. (experience)
- Experience shipping high volume DRAMs / SoCs. (experience)
- Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus. (experience)
- Experience working in a high-energy multi-disciplined engineering environment, strong at multi-tasking, and real-time crisis management. (experience)
- Excellent debugging skills. Proven track record to drive resolution of critical problems, while under pressure. (experience)
- Ability to understand complex technical discussions and extract action plans. (experience)
- Passionate to own/drive project development using well-defined metrics. (experience)
- Thrives in dynamic schedule driven development environment. (experience)
- Ability to succinctly summarize complex details for executive reporting. (experience)
- Extraordinary leadership skills and ability to encourage team members with a dedication to see the bigger picture (experience)
- Phenomenal leadership and social skills with a reciprocal approach. (experience)
Responsibilities
- The SoC DRAM Memory Subsystem Validation and Debug Program Manager will drive the memory subsystem readiness for our custom SoCs. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. The charter will include managing bring-up, validation, and the complicated debug of our groundbreaking memory subsystem. The EPM will also help craft the DRAM industry’s mobile roadmap and drive innovative DRAM technologies to accompany SoC’s across Apple’s product lines. In this multifaceted role, you will be the critical interface between Apple’s DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams to ensure these sophisticated memory technologies are delivered from architecture to mass production to Apple’s industry leading quality standards.
- Interface and drive memory related silicon issues across multi-functional teams: Design, Verification, Silicon Validation, Productization, System Hardware, and Software.
- Drive debug activities in post silicon environments, root-cause problems and steer the team to the best corrective action to move forward.
- Plan and lead adoption of DRAM technologies, custom package development and qualification process with multi-functional teams.
- Work closely with the DRAM Global Supply Management (GSM), DRAM & Package Engineering and SoC Program Management organizations to set priorities.
- Attend and drive technical sessions with DRAM vendors on new DRAM technology development to track and follow-up issues/action items and drive vendors to meet spec and schedule requirements.
- Work with DRAM GSM and silicon material management teams to plan and track distribution of new DRAM material across all systems in development.
- Enable tight collaboration between Design for Test (DFT), Product/Test/QA engineering, SiVal and Systems teams during NPI to finalize SoC performance targets and screen requirements.
- Drive internal program process to guarantee high quality silicon execution.
Tags & Categories
Answer 10 quick questions to check your fit for SoC DRAM Memory Subsystem Validation Engineering Program Manager @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs