SoC Hard IP Characterization Product Engineer
Apple
SoC Hard IP Characterization Product Engineer
Job Description
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. We are seeking a multifaceted engineer to develop system level test programs for debug, characterization, qualification and production of SoC devices! - Characterize parametric performance of High Speed IO PHYs (SERDES), PLLs, Sensors and other Custom HardIPs. - Define characterization plans, perform statistical data analysis, drive ATE-Bench correlation & data reviews across cross-functional teams and sign off on all silicon characterization activities. - Work with DFT and design teams to evaluate IP testability and drive new silicon debug. - Perform failure analysis to root-cause issues implement corrective actions and qualify cutting edge process technologies. - Work with Design, Validation, Test engineering, DFT, Program Management, and Manufacturing to support productization of next generation SoCs. - Complete yield and correlation analysis for all test insertions and support test time reduction related characterization activities.
Locations
- Austin, Texas, United States 78727
- Cupertino, California, United States 95014
- San Diego, California, United States 92128
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- characterizing parametric performance of High Speed IO PHYs (SERDES), PLLs, Sensors and Custom HardIPsintermediate
- defining characterization plansintermediate
- performing statistical data analysisintermediate
- driving ATE-Bench correlation and data reviewsintermediate
- signing off on silicon characterization activitiesintermediate
- evaluating IP testabilityintermediate
- driving new silicon debugintermediate
- performing failure analysisintermediate
- root-causing issuesintermediate
- implementing corrective actionsintermediate
- qualifying cutting edge process technologiesintermediate
- working with cross-functional teams (Design, Validation, Test engineering, DFT, Program Management, Manufacturing)intermediate
- completing yield and correlation analysisintermediate
- supporting test time reduction characterization activitiesintermediate
- developing system level test programs for debug, characterization, qualification and productionintermediate
Required Qualifications
- Bachelor's degree + 3 Years of Experience. (experience, 3 years)
Preferred Qualifications
- Understanding of Test and characterization of High-Speed IO PHYs, PLLs, Sensors and related electrical specifications (eye diagrams, JTOL, signal integrity, de-embedding etc.), mixed-signal IPs. (experience)
- Experience working with Digital, Mixed Signal, SOC Devices and a solid understanding of ATE production testing. Hands on ATE and/or Bench experience is a plus. (experience)
- Statistical data analysis tools to perform high volume characterization & production data analysis. (experience)
- High Speed Digital and Analog circuits, Design for Test and Manufacturing Concepts. (experience)
- Experience in scripting (Python, PERL etc.) is a plus. (experience)
Responsibilities
- - Characterize parametric performance of High Speed IO PHYs (SERDES), PLLs, Sensors and other Custom HardIPs.
- - Define characterization plans, perform statistical data analysis, drive ATE-Bench correlation & data reviews across cross-functional teams and sign off on all silicon characterization activities.
- - Work with DFT and design teams to evaluate IP testability and drive new silicon debug.
- - Perform failure analysis to root-cause issues implement corrective actions and qualify cutting edge process technologies.
- - Work with Design, Validation, Test engineering, DFT, Program Management, and Manufacturing to support productization of next generation SoCs.
- - Complete yield and correlation analysis for all test insertions and support test time reduction related characterization activities.
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SoC Hard IP Characterization Product Engineer
Apple
SoC Hard IP Characterization Product Engineer
Job Description
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. We are seeking a multifaceted engineer to develop system level test programs for debug, characterization, qualification and production of SoC devices! - Characterize parametric performance of High Speed IO PHYs (SERDES), PLLs, Sensors and other Custom HardIPs. - Define characterization plans, perform statistical data analysis, drive ATE-Bench correlation & data reviews across cross-functional teams and sign off on all silicon characterization activities. - Work with DFT and design teams to evaluate IP testability and drive new silicon debug. - Perform failure analysis to root-cause issues implement corrective actions and qualify cutting edge process technologies. - Work with Design, Validation, Test engineering, DFT, Program Management, and Manufacturing to support productization of next generation SoCs. - Complete yield and correlation analysis for all test insertions and support test time reduction related characterization activities.
Locations
- Austin, Texas, United States 78727
- Cupertino, California, United States 95014
- San Diego, California, United States 92128
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- characterizing parametric performance of High Speed IO PHYs (SERDES), PLLs, Sensors and Custom HardIPsintermediate
- defining characterization plansintermediate
- performing statistical data analysisintermediate
- driving ATE-Bench correlation and data reviewsintermediate
- signing off on silicon characterization activitiesintermediate
- evaluating IP testabilityintermediate
- driving new silicon debugintermediate
- performing failure analysisintermediate
- root-causing issuesintermediate
- implementing corrective actionsintermediate
- qualifying cutting edge process technologiesintermediate
- working with cross-functional teams (Design, Validation, Test engineering, DFT, Program Management, Manufacturing)intermediate
- completing yield and correlation analysisintermediate
- supporting test time reduction characterization activitiesintermediate
- developing system level test programs for debug, characterization, qualification and productionintermediate
Required Qualifications
- Bachelor's degree + 3 Years of Experience. (experience, 3 years)
Preferred Qualifications
- Understanding of Test and characterization of High-Speed IO PHYs, PLLs, Sensors and related electrical specifications (eye diagrams, JTOL, signal integrity, de-embedding etc.), mixed-signal IPs. (experience)
- Experience working with Digital, Mixed Signal, SOC Devices and a solid understanding of ATE production testing. Hands on ATE and/or Bench experience is a plus. (experience)
- Statistical data analysis tools to perform high volume characterization & production data analysis. (experience)
- High Speed Digital and Analog circuits, Design for Test and Manufacturing Concepts. (experience)
- Experience in scripting (Python, PERL etc.) is a plus. (experience)
Responsibilities
- - Characterize parametric performance of High Speed IO PHYs (SERDES), PLLs, Sensors and other Custom HardIPs.
- - Define characterization plans, perform statistical data analysis, drive ATE-Bench correlation & data reviews across cross-functional teams and sign off on all silicon characterization activities.
- - Work with DFT and design teams to evaluate IP testability and drive new silicon debug.
- - Perform failure analysis to root-cause issues implement corrective actions and qualify cutting edge process technologies.
- - Work with Design, Validation, Test engineering, DFT, Program Management, and Manufacturing to support productization of next generation SoCs.
- - Complete yield and correlation analysis for all test insertions and support test time reduction related characterization activities.
Tags & Categories
Answer 10 quick questions to check your fit for SoC Hard IP Characterization Product Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs