SoC Physical Design Engineer, PnR
Apple
SoC Physical Design Engineer, PnR
Job Description
We are seeking a seasoned Physical Design technical leader with deep expertise in high-performance & low-power design. In this highly visible role, you will work closely with cross-functional teams to come up with efficient chip and IP physical architecture taking into account physical design constraints early in the design cycle. - You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off. - You will also collaborate to drive methodologies and "best-known methods" to streamline PD work and develop guidelines and checklists. - You will be the primary technical contact for your focus area and are motivated to solve more challenging timing closure issues, area & power optimization etc.
Locations
- Austin, Texas, United States 78727
Salary
Estimated Salary Rangemedium confidence
30,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- high-performance designintermediate
- low-power designintermediate
- physical design implementationintermediate
- RTL2GDSintermediate
- PnRintermediate
- bump/RDLintermediate
- STAintermediate
- physical verificationintermediate
- EMIRintermediate
- sign-offintermediate
- timing closureintermediate
- area optimizationintermediate
- power optimizationintermediate
- cross-functional collaborationintermediate
- methodology developmentintermediate
- guideline creationintermediate
- checklist developmentintermediate
- problem-solvingintermediate
Required Qualifications
- Minimum BS and 3+ years of relevant industry experience (experience, 3 years)
Preferred Qualifications
- Knowledgeable in partition level P&R implementation including floorplanning, clock & power distribution, timing closure, and physical & electrical verification. (experience)
- Knowledge of PD construction & analysis flows and methodology. (experience)
- Strong interpersonal skills. (experience)
- Recent successful tapeouts in deep submicron technology. (experience)
- Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ. (experience)
- Shown ability to execute to stringent schedule & die size requirements. (experience)
- Experienced in industry standard tools and understanding their capabilities and underlying algorithms. (experience)
Responsibilities
- - You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off.
- - You will also collaborate to drive methodologies and "best-known methods" to streamline PD work and develop guidelines and checklists.
- - You will be the primary technical contact for your focus area and are motivated to solve more challenging timing closure issues, area & power optimization etc.
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Answer 10 quick questions to check your fit for SoC Physical Design Engineer, PnR @ Apple.
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SoC Physical Design Engineer, PnR
Apple
SoC Physical Design Engineer, PnR
Job Description
We are seeking a seasoned Physical Design technical leader with deep expertise in high-performance & low-power design. In this highly visible role, you will work closely with cross-functional teams to come up with efficient chip and IP physical architecture taking into account physical design constraints early in the design cycle. - You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off. - You will also collaborate to drive methodologies and "best-known methods" to streamline PD work and develop guidelines and checklists. - You will be the primary technical contact for your focus area and are motivated to solve more challenging timing closure issues, area & power optimization etc.
Locations
- Austin, Texas, United States 78727
Salary
Estimated Salary Rangemedium confidence
30,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- high-performance designintermediate
- low-power designintermediate
- physical design implementationintermediate
- RTL2GDSintermediate
- PnRintermediate
- bump/RDLintermediate
- STAintermediate
- physical verificationintermediate
- EMIRintermediate
- sign-offintermediate
- timing closureintermediate
- area optimizationintermediate
- power optimizationintermediate
- cross-functional collaborationintermediate
- methodology developmentintermediate
- guideline creationintermediate
- checklist developmentintermediate
- problem-solvingintermediate
Required Qualifications
- Minimum BS and 3+ years of relevant industry experience (experience, 3 years)
Preferred Qualifications
- Knowledgeable in partition level P&R implementation including floorplanning, clock & power distribution, timing closure, and physical & electrical verification. (experience)
- Knowledge of PD construction & analysis flows and methodology. (experience)
- Strong interpersonal skills. (experience)
- Recent successful tapeouts in deep submicron technology. (experience)
- Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ. (experience)
- Shown ability to execute to stringent schedule & die size requirements. (experience)
- Experienced in industry standard tools and understanding their capabilities and underlying algorithms. (experience)
Responsibilities
- - You will be responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off.
- - You will also collaborate to drive methodologies and "best-known methods" to streamline PD work and develop guidelines and checklists.
- - You will be the primary technical contact for your focus area and are motivated to solve more challenging timing closure issues, area & power optimization etc.
Tags & Categories
Answer 10 quick questions to check your fit for SoC Physical Design Engineer, PnR @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs