SoC Physical Design Engineer, PnR
Apple
SoC Physical Design Engineer, PnR
Job Description
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC applying innovative process technology. In Physical Design, you will be at the center of design effort collaborating with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs Knowledge of basic chip architecture, back end chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would include: - Working with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. - Completing netlist to GDS2 implementation for partition(s) meeting schedule and design goals. - Timing, physical and electrical verification, and driving the signoff closure for the partitions. - Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
Locations
- Waltham, Massachusetts, United States 02453
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- knowledge of basic chip architectureintermediate
- back end chip design flowintermediate
- physical synthesisintermediate
- floor-planningintermediate
- place and route (PnR)intermediate
- power gridintermediate
- timing (STA)intermediate
- physical design verification (DRC/LVS)intermediate
- EMIR (Redhawk/Totem/Voltus)intermediate
- netlist to GDS2 implementationintermediate
- timing verificationintermediate
- physical verificationintermediate
- electrical verificationintermediate
- signoff closureintermediate
- resolve design issuesintermediate
- improve design flowintermediate
- drive executionintermediate
- collaboration with architecture teamsintermediate
- collaboration with CAD teamsintermediate
- collaboration with timing teamsintermediate
- collaboration with logic design teamsintermediate
Required Qualifications
- Minimum BS Degree with 0+ years experience. (experience)
- Basic understanding of logic gates. (experience)
Preferred Qualifications
- Previous internship/co-op, project work or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design. (experience)
- Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields. (experience)
- Experience with Verilog, VHDL, Python, Perl, TCL and/or SPICE. (experience)
Responsibilities
- In Physical Design, you will be at the center of design effort collaborating with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs Knowledge of basic chip architecture, back end chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would include:
- - Working with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
- - Completing netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
- - Timing, physical and electrical verification, and driving the signoff closure for the partitions.
- - Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
Tags & Categories
Answer 10 quick questions to check your fit for SoC Physical Design Engineer, PnR @ Apple.
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SoC Physical Design Engineer, PnR
Apple
SoC Physical Design Engineer, PnR
Job Description
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC applying innovative process technology. In Physical Design, you will be at the center of design effort collaborating with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs Knowledge of basic chip architecture, back end chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would include: - Working with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. - Completing netlist to GDS2 implementation for partition(s) meeting schedule and design goals. - Timing, physical and electrical verification, and driving the signoff closure for the partitions. - Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
Locations
- Waltham, Massachusetts, United States 02453
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- knowledge of basic chip architectureintermediate
- back end chip design flowintermediate
- physical synthesisintermediate
- floor-planningintermediate
- place and route (PnR)intermediate
- power gridintermediate
- timing (STA)intermediate
- physical design verification (DRC/LVS)intermediate
- EMIR (Redhawk/Totem/Voltus)intermediate
- netlist to GDS2 implementationintermediate
- timing verificationintermediate
- physical verificationintermediate
- electrical verificationintermediate
- signoff closureintermediate
- resolve design issuesintermediate
- improve design flowintermediate
- drive executionintermediate
- collaboration with architecture teamsintermediate
- collaboration with CAD teamsintermediate
- collaboration with timing teamsintermediate
- collaboration with logic design teamsintermediate
Required Qualifications
- Minimum BS Degree with 0+ years experience. (experience)
- Basic understanding of logic gates. (experience)
Preferred Qualifications
- Previous internship/co-op, project work or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design. (experience)
- Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields. (experience)
- Experience with Verilog, VHDL, Python, Perl, TCL and/or SPICE. (experience)
Responsibilities
- In Physical Design, you will be at the center of design effort collaborating with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs Knowledge of basic chip architecture, back end chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would include:
- - Working with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
- - Completing netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
- - Timing, physical and electrical verification, and driving the signoff closure for the partitions.
- - Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
Tags & Categories
Answer 10 quick questions to check your fit for SoC Physical Design Engineer, PnR @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs