SoC Power Flow Methodology Engineer
Apple
SoC Power Flow Methodology Engineer
Job Description
Do you love creating solutions for complex challenges? As part of the Low Power group within Silicon Technologies, you’ll help deliver cutting-edge new technology and capabilities for low-power chip design that fuels Apple’s next-generation chips! In this role, as a member of our dynamic group, you will be responsible for the development and enhancement of our low-power flows, providing designers new capabilities in terms of power domains unseen in previous chips, while working on highly visible products used by millions of people every day! As a Power Flow Methodology Engineer, you’ll deliver new automated solutions and capabilities for the Silicon Engineering Power team to build chips that are more power efficient than ever before. You will help with the architecture, implementation, and verification of new low-power design and verification flows and help to craft the low-power methodologies across a wide variety of future technologies. The work involves creating flows and tools related to power analysis, optimization and verification which may be run as part of RTL construction/verification, synthesis, or P&R. Additional responsibilities include communicating with the design team to answer questions about the materials and drive issues to resolution.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
30,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- low-power chip designintermediate
- development and enhancement of low-power flowsintermediate
- power analysisintermediate
- power optimizationintermediate
- power verificationintermediate
- RTL constructionintermediate
- RTL verificationintermediate
- synthesisintermediate
- Place and Route (P&R)intermediate
- architecture of low-power design flowsintermediate
- implementation of low-power design flowsintermediate
- verification of low-power design flowsintermediate
- crafting low-power methodologiesintermediate
- communicating with design teamsintermediate
- driving issues to resolutionintermediate
Required Qualifications
- Minimum requirement of a Bachelors Degree in a relevant field (degree in a relevant field)
Preferred Qualifications
- Good understanding of VLSI designs and SOC design flows. (experience)
- Strong passion for scripting and applying low-power domain-specific knowledge to create new software solutions. (experience)
- Strong background with flow development and/or object-oriented language algorithm design such as Python / C++ / Java. (experience)
- Solid understanding and proven track record using modern software testing and development practices. (experience)
- Good written/verbal communications skills are required. (experience)
- Knowledge of Tcl / Perl, experience with EDA tools, GUI development, and/or low-power concepts such as UPF and low-power design is a plus. (experience)
Responsibilities
- As a Power Flow Methodology Engineer, you’ll deliver new automated solutions and capabilities for the Silicon Engineering Power team to build chips that are more power efficient than ever before. You will help with the architecture, implementation, and verification of new low-power design and verification flows and help to craft the low-power methodologies across a wide variety of future technologies.
- The work involves creating flows and tools related to power analysis, optimization and verification which may be run as part of RTL construction/verification, synthesis, or P&R.
- Additional responsibilities include communicating with the design team to answer questions about the materials and drive issues to resolution.
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Answer 10 quick questions to check your fit for SoC Power Flow Methodology Engineer @ Apple.
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SoC Power Flow Methodology Engineer
Apple
SoC Power Flow Methodology Engineer
Job Description
Do you love creating solutions for complex challenges? As part of the Low Power group within Silicon Technologies, you’ll help deliver cutting-edge new technology and capabilities for low-power chip design that fuels Apple’s next-generation chips! In this role, as a member of our dynamic group, you will be responsible for the development and enhancement of our low-power flows, providing designers new capabilities in terms of power domains unseen in previous chips, while working on highly visible products used by millions of people every day! As a Power Flow Methodology Engineer, you’ll deliver new automated solutions and capabilities for the Silicon Engineering Power team to build chips that are more power efficient than ever before. You will help with the architecture, implementation, and verification of new low-power design and verification flows and help to craft the low-power methodologies across a wide variety of future technologies. The work involves creating flows and tools related to power analysis, optimization and verification which may be run as part of RTL construction/verification, synthesis, or P&R. Additional responsibilities include communicating with the design team to answer questions about the materials and drive issues to resolution.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
30,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- low-power chip designintermediate
- development and enhancement of low-power flowsintermediate
- power analysisintermediate
- power optimizationintermediate
- power verificationintermediate
- RTL constructionintermediate
- RTL verificationintermediate
- synthesisintermediate
- Place and Route (P&R)intermediate
- architecture of low-power design flowsintermediate
- implementation of low-power design flowsintermediate
- verification of low-power design flowsintermediate
- crafting low-power methodologiesintermediate
- communicating with design teamsintermediate
- driving issues to resolutionintermediate
Required Qualifications
- Minimum requirement of a Bachelors Degree in a relevant field (degree in a relevant field)
Preferred Qualifications
- Good understanding of VLSI designs and SOC design flows. (experience)
- Strong passion for scripting and applying low-power domain-specific knowledge to create new software solutions. (experience)
- Strong background with flow development and/or object-oriented language algorithm design such as Python / C++ / Java. (experience)
- Solid understanding and proven track record using modern software testing and development practices. (experience)
- Good written/verbal communications skills are required. (experience)
- Knowledge of Tcl / Perl, experience with EDA tools, GUI development, and/or low-power concepts such as UPF and low-power design is a plus. (experience)
Responsibilities
- As a Power Flow Methodology Engineer, you’ll deliver new automated solutions and capabilities for the Silicon Engineering Power team to build chips that are more power efficient than ever before. You will help with the architecture, implementation, and verification of new low-power design and verification flows and help to craft the low-power methodologies across a wide variety of future technologies.
- The work involves creating flows and tools related to power analysis, optimization and verification which may be run as part of RTL construction/verification, synthesis, or P&R.
- Additional responsibilities include communicating with the design team to answer questions about the materials and drive issues to resolution.
Tags & Categories
Answer 10 quick questions to check your fit for SoC Power Flow Methodology Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs