SoC Power Modeling Engineer
Apple
SoC Power Modeling Engineer
Job Description
Do you have a passion for crafting new solutions? As part of our Silicon Engineering group, you will generate ideas and turn them into reality. You will be part of the team responsible for designing state-of-the-art ASICs that are integral to many Apple products. We are looking for an engineer who will work on the modeling of power dissipation of various IPs including AI/ML and the corresponding power rails, peak current requirements and voltage-frequency operating points for upcoming generations of Apple SOCs. This role provides an opportunity to participate in optimization of a variety of leading edge chips for power-efficiency. You will collaborate across many teams including architecture, design, thermals, PMIC and system design to model power and current profiles for various IPs of the SOC, and the voltages-frequency operating points. The job also involves partnering with the lab and silicon characterization/validation and technology teams on correlating the models to the HW data. Imagine yourself collaborating across many fields, playing a decisive role of getting innovative products to millions of customers! You will have the opportunity to build new insights into silicon optimization, as well as work with a team of hardworking engineers and be involved in HW/model correlation efforts of mobile SoC design. Your main responsibilities will be: - Modeling power dissipation and power delivery, - Establishing voltages for DVFM states of IPs, including Neural Engines, CPUs, Graphics, compute (AI/ML) accelerators, media IPs, caches and fabric. - Modeling power dissipation for customer use-cases. - Interacting with the Technology team, Silicon Validation, and Product Engineering teams to establish voltage-frequency design points pre- and post- silicon. - Working with the power lab and test teams to correlate models to HW data.
Locations
- San Diego, California, United States 92128
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- modeling power dissipationintermediate
- modeling power deliveryintermediate
- establishing voltages for DVFM statesintermediate
- modeling power dissipation for customer use-casesintermediate
- interacting with Technology teamintermediate
- interacting with Silicon Validation teamintermediate
- interacting with Product Engineering teamsintermediate
- establishing voltage-frequency design pointsintermediate
- correlating models to HW dataintermediate
- working with power lab and test teamsintermediate
- ASIC designintermediate
- SoC designintermediate
- power-efficiency optimizationintermediate
- collaboration across teamsintermediate
- silicon characterizationintermediate
- silicon validationintermediate
- HW/model correlationintermediate
- AI/ML knowledgeintermediate
- Neural Engines knowledgeintermediate
- CPUs knowledgeintermediate
- Graphics knowledgeintermediate
- compute accelerators knowledgeintermediate
- media IPs knowledgeintermediate
- caches knowledgeintermediate
- fabric knowledgeintermediate
Required Qualifications
- A minimum of a bachelor's degree in relevant field and a minimum of 10 years of relevant industry experience. (experience, 10 years)
Preferred Qualifications
- Our ideal candidate should have 3+ years relevant experience, programming skills and an understanding of low-power digital design and power fundamentals. You should also have the following: (experience, 3 years)
- Understanding of SOC power modeling and current demand. (experience)
- Understanding of electrical properties of on-die PDN, power gating, package and system power delivery. (experience)
- Skills in scripting, data analysis and experience with EDA tools. (experience)
- Understanding of VLSI design flow and CMOS technology. (experience)
- Extensive background in EE. (experience)
- Ability to understand and model thermal control loops and throttling mechanisms. (experience)
- Familiarity with physical design tools for power optimization. (experience)
- Great teammate and excellent communication skills. (experience)
Responsibilities
- Imagine yourself collaborating across many fields, playing a decisive role of getting innovative products to millions of customers! You will have the opportunity to build new insights into silicon optimization, as well as work with a team of hardworking engineers and be involved in HW/model correlation efforts of mobile SoC design. Your main responsibilities will be:
- - Modeling power dissipation and power delivery,
- - Establishing voltages for DVFM states of IPs, including Neural Engines, CPUs, Graphics, compute (AI/ML) accelerators, media IPs, caches and fabric.
- - Modeling power dissipation for customer use-cases.
- - Interacting with the Technology team, Silicon Validation, and Product Engineering teams to establish voltage-frequency design points pre- and post- silicon.
- - Working with the power lab and test teams to correlate models to HW data.
Tags & Categories
Answer 10 quick questions to check your fit for SoC Power Modeling Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs
SoC Power Modeling Engineer
Apple
SoC Power Modeling Engineer
Job Description
Do you have a passion for crafting new solutions? As part of our Silicon Engineering group, you will generate ideas and turn them into reality. You will be part of the team responsible for designing state-of-the-art ASICs that are integral to many Apple products. We are looking for an engineer who will work on the modeling of power dissipation of various IPs including AI/ML and the corresponding power rails, peak current requirements and voltage-frequency operating points for upcoming generations of Apple SOCs. This role provides an opportunity to participate in optimization of a variety of leading edge chips for power-efficiency. You will collaborate across many teams including architecture, design, thermals, PMIC and system design to model power and current profiles for various IPs of the SOC, and the voltages-frequency operating points. The job also involves partnering with the lab and silicon characterization/validation and technology teams on correlating the models to the HW data. Imagine yourself collaborating across many fields, playing a decisive role of getting innovative products to millions of customers! You will have the opportunity to build new insights into silicon optimization, as well as work with a team of hardworking engineers and be involved in HW/model correlation efforts of mobile SoC design. Your main responsibilities will be: - Modeling power dissipation and power delivery, - Establishing voltages for DVFM states of IPs, including Neural Engines, CPUs, Graphics, compute (AI/ML) accelerators, media IPs, caches and fabric. - Modeling power dissipation for customer use-cases. - Interacting with the Technology team, Silicon Validation, and Product Engineering teams to establish voltage-frequency design points pre- and post- silicon. - Working with the power lab and test teams to correlate models to HW data.
Locations
- San Diego, California, United States 92128
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- modeling power dissipationintermediate
- modeling power deliveryintermediate
- establishing voltages for DVFM statesintermediate
- modeling power dissipation for customer use-casesintermediate
- interacting with Technology teamintermediate
- interacting with Silicon Validation teamintermediate
- interacting with Product Engineering teamsintermediate
- establishing voltage-frequency design pointsintermediate
- correlating models to HW dataintermediate
- working with power lab and test teamsintermediate
- ASIC designintermediate
- SoC designintermediate
- power-efficiency optimizationintermediate
- collaboration across teamsintermediate
- silicon characterizationintermediate
- silicon validationintermediate
- HW/model correlationintermediate
- AI/ML knowledgeintermediate
- Neural Engines knowledgeintermediate
- CPUs knowledgeintermediate
- Graphics knowledgeintermediate
- compute accelerators knowledgeintermediate
- media IPs knowledgeintermediate
- caches knowledgeintermediate
- fabric knowledgeintermediate
Required Qualifications
- A minimum of a bachelor's degree in relevant field and a minimum of 10 years of relevant industry experience. (experience, 10 years)
Preferred Qualifications
- Our ideal candidate should have 3+ years relevant experience, programming skills and an understanding of low-power digital design and power fundamentals. You should also have the following: (experience, 3 years)
- Understanding of SOC power modeling and current demand. (experience)
- Understanding of electrical properties of on-die PDN, power gating, package and system power delivery. (experience)
- Skills in scripting, data analysis and experience with EDA tools. (experience)
- Understanding of VLSI design flow and CMOS technology. (experience)
- Extensive background in EE. (experience)
- Ability to understand and model thermal control loops and throttling mechanisms. (experience)
- Familiarity with physical design tools for power optimization. (experience)
- Great teammate and excellent communication skills. (experience)
Responsibilities
- Imagine yourself collaborating across many fields, playing a decisive role of getting innovative products to millions of customers! You will have the opportunity to build new insights into silicon optimization, as well as work with a team of hardworking engineers and be involved in HW/model correlation efforts of mobile SoC design. Your main responsibilities will be:
- - Modeling power dissipation and power delivery,
- - Establishing voltages for DVFM states of IPs, including Neural Engines, CPUs, Graphics, compute (AI/ML) accelerators, media IPs, caches and fabric.
- - Modeling power dissipation for customer use-cases.
- - Interacting with the Technology team, Silicon Validation, and Product Engineering teams to establish voltage-frequency design points pre- and post- silicon.
- - Working with the power lab and test teams to correlate models to HW data.
Tags & Categories
Answer 10 quick questions to check your fit for SoC Power Modeling Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs