SoC RTL Design Engineer
Apple
SoC RTL Design Engineer
Job Description
At Apple, phenomenal ideas have a way of becoming great products and customer experiences very quickly. The industry is accustomed to Apple taping out the SOC’s for our various products at a rigorous pace. In order to achieve this, Apple’s best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high transparency and critically important role and requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel to hit schedules consistently with a quality design. Our position requires in-depth knowledge of the chip micro-architecture and digital logic design.. - Work with architecture team to define the design microarchitecture hierarchy and interfaces and develop microarchitecture spec. Refine the spec with reviews with other teams - Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Own all aspects of RTL development design. - Work and collaborate with other designers in the group to deliver results. - Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block - Work with front-end synthesis/STA teams to ensure timing for the block is met - Work with power/performance and functional verification team to ensure high quality of the block - Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process
Locations
- Austin, Texas, United States 78727
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 5,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- chip micro-architecture knowledgeintermediate
- digital logic designintermediate
- microarchitecture specification developmentintermediate
- RTL designintermediate
- RTL developmentintermediate
- collaboration with designersintermediate
- IP block integrationintermediate
- memory optimizationintermediate
- hard macro optimizationintermediate
- front-end synthesisintermediate
- static timing analysis (STA)intermediate
- timing closureintermediate
- power analysisintermediate
- performance analysisintermediate
- functional verificationintermediate
- multi-disciplinary collaborationintermediate
- design quality assuranceintermediate
- task coordinationintermediate
- parallel task managementintermediate
- schedule adherenceintermediate
Required Qualifications
- Minimum of BS + 10 years relevant industry experience (experience, 10 years)
Preferred Qualifications
- A consistent track record of dedication designs in high volume production for low power applications (experience)
- Experience in driving microarchitecture and developing specification for logic designs (experience)
- Consistent record of RTL design on large sophisticated designs (experience)
- Solid working experience with synthesis, power, performance and verification team to develop and deliver high quality RTL design timely (experience)
- Strong interpersonal skills are a must, as the candidate will talk to a lot of diverse groups within the company (experience)
- Self-starter, highly motivated, highly organized, and schedule driven is a must (experience)
- Familiarity with all front-end tools including lint, CDC, synthesis is a plus (experience)
- Knowledge of high speed DRAM memory controller design or interconnect design is highly preferable. (experience)
Responsibilities
- - Work with architecture team to define the design microarchitecture hierarchy and interfaces and develop microarchitecture spec. Refine the spec with reviews with other teams
- - Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Own all aspects of RTL development design.
- - Work and collaborate with other designers in the group to deliver results.
- - Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block
- - Work with front-end synthesis/STA teams to ensure timing for the block is met
- - Work with power/performance and functional verification team to ensure high quality of the block
- - Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process
Tags & Categories
Answer 10 quick questions to check your fit for SoC RTL Design Engineer @ Apple.
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SoC RTL Design Engineer
Apple
SoC RTL Design Engineer
Job Description
At Apple, phenomenal ideas have a way of becoming great products and customer experiences very quickly. The industry is accustomed to Apple taping out the SOC’s for our various products at a rigorous pace. In order to achieve this, Apple’s best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high transparency and critically important role and requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel to hit schedules consistently with a quality design. Our position requires in-depth knowledge of the chip micro-architecture and digital logic design.. - Work with architecture team to define the design microarchitecture hierarchy and interfaces and develop microarchitecture spec. Refine the spec with reviews with other teams - Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Own all aspects of RTL development design. - Work and collaborate with other designers in the group to deliver results. - Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block - Work with front-end synthesis/STA teams to ensure timing for the block is met - Work with power/performance and functional verification team to ensure high quality of the block - Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process
Locations
- Austin, Texas, United States 78727
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 5,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- chip micro-architecture knowledgeintermediate
- digital logic designintermediate
- microarchitecture specification developmentintermediate
- RTL designintermediate
- RTL developmentintermediate
- collaboration with designersintermediate
- IP block integrationintermediate
- memory optimizationintermediate
- hard macro optimizationintermediate
- front-end synthesisintermediate
- static timing analysis (STA)intermediate
- timing closureintermediate
- power analysisintermediate
- performance analysisintermediate
- functional verificationintermediate
- multi-disciplinary collaborationintermediate
- design quality assuranceintermediate
- task coordinationintermediate
- parallel task managementintermediate
- schedule adherenceintermediate
Required Qualifications
- Minimum of BS + 10 years relevant industry experience (experience, 10 years)
Preferred Qualifications
- A consistent track record of dedication designs in high volume production for low power applications (experience)
- Experience in driving microarchitecture and developing specification for logic designs (experience)
- Consistent record of RTL design on large sophisticated designs (experience)
- Solid working experience with synthesis, power, performance and verification team to develop and deliver high quality RTL design timely (experience)
- Strong interpersonal skills are a must, as the candidate will talk to a lot of diverse groups within the company (experience)
- Self-starter, highly motivated, highly organized, and schedule driven is a must (experience)
- Familiarity with all front-end tools including lint, CDC, synthesis is a plus (experience)
- Knowledge of high speed DRAM memory controller design or interconnect design is highly preferable. (experience)
Responsibilities
- - Work with architecture team to define the design microarchitecture hierarchy and interfaces and develop microarchitecture spec. Refine the spec with reviews with other teams
- - Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Own all aspects of RTL development design.
- - Work and collaborate with other designers in the group to deliver results.
- - Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block
- - Work with front-end synthesis/STA teams to ensure timing for the block is met
- - Work with power/performance and functional verification team to ensure high quality of the block
- - Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process
Tags & Categories
Answer 10 quick questions to check your fit for SoC RTL Design Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs