SOC Verification Engineer
Apple
SOC Verification Engineer
Job Description
Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. The SOC Verification Engineer will be responsible for pre-silicon RTL verification of block and top level SOC. With deep understanding of SOC architecture and meticulous attention to details, you will interact with all disciplines to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification. Understand details of microarchitecture and build block / chip level testbench using best-in-class verification methodology. Create verification plan from specification and in coordination with architects. Generate directed and ingenuous constrained random tests. Create/analyze coverage model and enhance testbench/test to increase coverage. Build automated flows for block and chip level verification. Debug failures, manage bug tracking, and close coverage. Hold detailed verification reviews and set standard for coding quality. Work closely with team members to improve methodology and flow.
Locations
- San Francisco Bay Area, California, United States
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- SOC architecture understandingintermediate
- attention to detailsintermediate
- develop reusable testbenchintermediate
- verification environment developmentintermediate
- metric driven verificationintermediate
- microarchitecture understandingintermediate
- build block/chip level testbenchintermediate
- verification methodologyintermediate
- create verification planintermediate
- generate directed testsintermediate
- generate constrained random testsintermediate
- create/analyze coverage modelintermediate
- enhance testbench/testintermediate
- build automated flowsintermediate
- debug failuresintermediate
- manage bug trackingintermediate
- close coverageintermediate
- hold verification reviewsintermediate
- set coding quality standardsintermediate
- improve methodology and flowintermediate
- team collaborationintermediate
Required Qualifications
- Solid fundamentals in Verilog and SystemVerilog for verification. (experience)
- Basic knowledge of UVM methodology. (experience)
- Solid verification skills in problem solving and debugging. (experience)
- Experience with Constrained Random testing is a plus. (experience)
- Good understanding of overall verification flow (experience)
- Knowledge of industry standard interfaces like I2C, UART, SPI. (experience)
- Understanding and usage of System Verilog Assertion (SVA) (experience)
- Programing experience in C (experience)
- Experience writing scripts in languages such as Perl or Python a plus. (experience)
- Should be a great teammate with excellent communication skills and the desire to take on diverse challenges. (experience)
Preferred Qualifications
- Typically requires MSEE with 0-3+ years of experience (experience, 3 years)
Responsibilities
- Understand details of microarchitecture and build block / chip level testbench using best-in-class verification methodology.
- Create verification plan from specification and in coordination with architects.
- Generate directed and ingenuous constrained random tests.
- Create/analyze coverage model and enhance testbench/test to increase coverage.
- Build automated flows for block and chip level verification.
- Debug failures, manage bug tracking, and close coverage.
- Hold detailed verification reviews and set standard for coding quality.
- Work closely with team members to improve methodology and flow.
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Answer 10 quick questions to check your fit for SOC Verification Engineer @ Apple.
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SOC Verification Engineer
Apple
SOC Verification Engineer
Job Description
Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. The SOC Verification Engineer will be responsible for pre-silicon RTL verification of block and top level SOC. With deep understanding of SOC architecture and meticulous attention to details, you will interact with all disciplines to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification. Understand details of microarchitecture and build block / chip level testbench using best-in-class verification methodology. Create verification plan from specification and in coordination with architects. Generate directed and ingenuous constrained random tests. Create/analyze coverage model and enhance testbench/test to increase coverage. Build automated flows for block and chip level verification. Debug failures, manage bug tracking, and close coverage. Hold detailed verification reviews and set standard for coding quality. Work closely with team members to improve methodology and flow.
Locations
- San Francisco Bay Area, California, United States
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- SOC architecture understandingintermediate
- attention to detailsintermediate
- develop reusable testbenchintermediate
- verification environment developmentintermediate
- metric driven verificationintermediate
- microarchitecture understandingintermediate
- build block/chip level testbenchintermediate
- verification methodologyintermediate
- create verification planintermediate
- generate directed testsintermediate
- generate constrained random testsintermediate
- create/analyze coverage modelintermediate
- enhance testbench/testintermediate
- build automated flowsintermediate
- debug failuresintermediate
- manage bug trackingintermediate
- close coverageintermediate
- hold verification reviewsintermediate
- set coding quality standardsintermediate
- improve methodology and flowintermediate
- team collaborationintermediate
Required Qualifications
- Solid fundamentals in Verilog and SystemVerilog for verification. (experience)
- Basic knowledge of UVM methodology. (experience)
- Solid verification skills in problem solving and debugging. (experience)
- Experience with Constrained Random testing is a plus. (experience)
- Good understanding of overall verification flow (experience)
- Knowledge of industry standard interfaces like I2C, UART, SPI. (experience)
- Understanding and usage of System Verilog Assertion (SVA) (experience)
- Programing experience in C (experience)
- Experience writing scripts in languages such as Perl or Python a plus. (experience)
- Should be a great teammate with excellent communication skills and the desire to take on diverse challenges. (experience)
Preferred Qualifications
- Typically requires MSEE with 0-3+ years of experience (experience, 3 years)
Responsibilities
- Understand details of microarchitecture and build block / chip level testbench using best-in-class verification methodology.
- Create verification plan from specification and in coordination with architects.
- Generate directed and ingenuous constrained random tests.
- Create/analyze coverage model and enhance testbench/test to increase coverage.
- Build automated flows for block and chip level verification.
- Debug failures, manage bug tracking, and close coverage.
- Hold detailed verification reviews and set standard for coding quality.
- Work closely with team members to improve methodology and flow.
Tags & Categories
Answer 10 quick questions to check your fit for SOC Verification Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs