STA engineer
Apple
STA engineer
Job Description
We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams. You will be responsible for: Develop/support automated block and full chip level signoff flows Full Chip Timing/Noise convergence and full signoff for high quality TO Enable hierarchical Timing flows Power optimizations Generate block level budget and context for correlation with Full Chip Drive custom IP integration and custom timing checks flows Close work with Design, DFT, architecture and Power team
Locations
- Herzliya, Tel Aviv District, Israel
Salary
Estimated Salary Rangemedium confidence
1,500,000 - 3,500,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- develop automated signoff flowsintermediate
- full chip timing convergenceintermediate
- full chip noise convergenceintermediate
- full signoff for high quality TOintermediate
- enable hierarchical timing flowsintermediate
- power optimizationsintermediate
- generate block level budget and contextintermediate
- drive custom IP integrationintermediate
- custom timing checks flowsintermediate
- close work with design teamintermediate
- close work with DFT teamintermediate
- close work with architecture teamintermediate
- close work with power teamintermediate
Required Qualifications
- 4+ years experience in Static Timing analysis (experience, 4 years)
- Extensive experience with one of the commercial STA tools (experience)
- Familiarity with hierarchical design approach, top-down design, timing and physical convergence (experience)
- Experience with backend STA closure and Signoff (experience)
- Deep understanding of designs' constraints development (experience)
- Good understanding of AC timing from specs to implementation (experience)
- Good understanding of DFT modes and their constraints (experience)
- Good communication skills and team player (experience)
- Quick learning of flows and methods (experience)
Preferred Qualifications
- Advantage - Understanding noise and signal integrity effects (experience)
- Advantage - Timing margins fundamental from synthesis to signoff (experience)
- Advantage - Experience with scripting (experience)
Responsibilities
- You will be responsible for:
- Develop/support automated block and full chip level signoff flows
- Full Chip Timing/Noise convergence and full signoff for high quality TO
- Enable hierarchical Timing flows
- Power optimizations
- Generate block level budget and context for correlation with Full Chip
- Drive custom IP integration and custom timing checks flows
- Close work with Design, DFT, architecture and Power team
Tags & Categories
Answer 10 quick questions to check your fit for STA engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs
STA engineer
Apple
STA engineer
Job Description
We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams. You will be responsible for: Develop/support automated block and full chip level signoff flows Full Chip Timing/Noise convergence and full signoff for high quality TO Enable hierarchical Timing flows Power optimizations Generate block level budget and context for correlation with Full Chip Drive custom IP integration and custom timing checks flows Close work with Design, DFT, architecture and Power team
Locations
- Herzliya, Tel Aviv District, Israel
Salary
Estimated Salary Rangemedium confidence
1,500,000 - 3,500,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- develop automated signoff flowsintermediate
- full chip timing convergenceintermediate
- full chip noise convergenceintermediate
- full signoff for high quality TOintermediate
- enable hierarchical timing flowsintermediate
- power optimizationsintermediate
- generate block level budget and contextintermediate
- drive custom IP integrationintermediate
- custom timing checks flowsintermediate
- close work with design teamintermediate
- close work with DFT teamintermediate
- close work with architecture teamintermediate
- close work with power teamintermediate
Required Qualifications
- 4+ years experience in Static Timing analysis (experience, 4 years)
- Extensive experience with one of the commercial STA tools (experience)
- Familiarity with hierarchical design approach, top-down design, timing and physical convergence (experience)
- Experience with backend STA closure and Signoff (experience)
- Deep understanding of designs' constraints development (experience)
- Good understanding of AC timing from specs to implementation (experience)
- Good understanding of DFT modes and their constraints (experience)
- Good communication skills and team player (experience)
- Quick learning of flows and methods (experience)
Preferred Qualifications
- Advantage - Understanding noise and signal integrity effects (experience)
- Advantage - Timing margins fundamental from synthesis to signoff (experience)
- Advantage - Experience with scripting (experience)
Responsibilities
- You will be responsible for:
- Develop/support automated block and full chip level signoff flows
- Full Chip Timing/Noise convergence and full signoff for high quality TO
- Enable hierarchical Timing flows
- Power optimizations
- Generate block level budget and context for correlation with Full Chip
- Drive custom IP integration and custom timing checks flows
- Close work with Design, DFT, architecture and Power team
Tags & Categories
Answer 10 quick questions to check your fit for STA engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs