STA (Static Timing Analysis) Engineer - Advanced Technologies Group
Apple
STA (Static Timing Analysis) Engineer - Advanced Technologies Group
Job Description
At Apple, we relentlessly strive to create products that enrich people’s lives. Are you passionate about solving unresolved challenges and revolutionizing the industry? We have an exceptional opportunity for an exceptionally talented IP timing lead to join our dynamic group. As a key member of this team, you will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of Apple customers daily. This role is for an IP timing Engineer who will empower us to produce fully functional first silicon IP designs. Your responsibilities will encompass all phases of pre-silicon development, from defining the constraints to achieving high-quality tape-out. In this role, you will be responsible for developing and owning IP-level Netlist generation (Synthesis, UPF, scan insertion, external IP’s integration) & timing constraints, for both regular and custom requirements, from synthesis to sign-off, ensuring sign-off quality timing convergence. You will collaborate closely with the RTL designer to comprehend the design intent and clock structure, with the CAD team to understand and develop the flow, and with the Physical Design team to finalize and sign off on the timing. Additionally, you will actively contribute by generating ideas and plans to verify your own timing constraints. You will demonstrate innovation in timing constraints and flow to facilitate timing closure and address any potential pessimism or fallouts in timing analysis.
Locations
- Herzliya, Tel Aviv District, Israel
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- IP timing analysisintermediate
- Netlist generationintermediate
- Synthesisintermediate
- UPFintermediate
- Scan insertionintermediate
- External IP integrationintermediate
- Timing constraints developmentintermediate
- RTL design collaborationintermediate
- CAD flow developmentintermediate
- Physical Design collaborationintermediate
- Timing sign-offintermediate
- Timing closureintermediate
- Timing analysisintermediate
- Innovation in timing constraintsintermediate
Required Qualifications
- 5+ years of experience in the field (experience, 5 years)
- At least 2+ years of experience in writing ASIC timing constraints and achieving timing closure (experience, 2 years)
- Expertise in STA tools (Primetime) and flow generation (experience)
- Knowledge of the ASIC design timing closure flow and methodology (experience)
Preferred Qualifications
- Understanding of timing corners/modes (experience)
- Familiarity with process variations and signal integrity-related issues (experience)
- Hands-on experience in generating and managing timing/SDC constraints, proficient in scripting languages (Tcl and Perl) (experience)
- Knowledge of synthesis, DFT, and backend-related methodologies and tools (experience)
- Strong communication skills are required, as you will interact with various groups (experience)
Responsibilities
- In this role, you will be responsible for developing and owning IP-level Netlist generation (Synthesis, UPF, scan insertion, external IP’s integration) & timing constraints, for both regular and custom requirements, from synthesis to sign-off, ensuring sign-off quality timing convergence. You will collaborate closely with the RTL designer to comprehend the design intent and clock structure, with the CAD team to understand and develop the flow, and with the Physical Design team to finalize and sign off on the timing. Additionally, you will actively contribute by generating ideas and plans to verify your own timing constraints. You will demonstrate innovation in timing constraints and flow to facilitate timing closure and address any potential pessimism or fallouts in timing analysis.
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STA (Static Timing Analysis) Engineer - Advanced Technologies Group
Apple
STA (Static Timing Analysis) Engineer - Advanced Technologies Group
Job Description
At Apple, we relentlessly strive to create products that enrich people’s lives. Are you passionate about solving unresolved challenges and revolutionizing the industry? We have an exceptional opportunity for an exceptionally talented IP timing lead to join our dynamic group. As a key member of this team, you will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of Apple customers daily. This role is for an IP timing Engineer who will empower us to produce fully functional first silicon IP designs. Your responsibilities will encompass all phases of pre-silicon development, from defining the constraints to achieving high-quality tape-out. In this role, you will be responsible for developing and owning IP-level Netlist generation (Synthesis, UPF, scan insertion, external IP’s integration) & timing constraints, for both regular and custom requirements, from synthesis to sign-off, ensuring sign-off quality timing convergence. You will collaborate closely with the RTL designer to comprehend the design intent and clock structure, with the CAD team to understand and develop the flow, and with the Physical Design team to finalize and sign off on the timing. Additionally, you will actively contribute by generating ideas and plans to verify your own timing constraints. You will demonstrate innovation in timing constraints and flow to facilitate timing closure and address any potential pessimism or fallouts in timing analysis.
Locations
- Herzliya, Tel Aviv District, Israel
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 50,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- IP timing analysisintermediate
- Netlist generationintermediate
- Synthesisintermediate
- UPFintermediate
- Scan insertionintermediate
- External IP integrationintermediate
- Timing constraints developmentintermediate
- RTL design collaborationintermediate
- CAD flow developmentintermediate
- Physical Design collaborationintermediate
- Timing sign-offintermediate
- Timing closureintermediate
- Timing analysisintermediate
- Innovation in timing constraintsintermediate
Required Qualifications
- 5+ years of experience in the field (experience, 5 years)
- At least 2+ years of experience in writing ASIC timing constraints and achieving timing closure (experience, 2 years)
- Expertise in STA tools (Primetime) and flow generation (experience)
- Knowledge of the ASIC design timing closure flow and methodology (experience)
Preferred Qualifications
- Understanding of timing corners/modes (experience)
- Familiarity with process variations and signal integrity-related issues (experience)
- Hands-on experience in generating and managing timing/SDC constraints, proficient in scripting languages (Tcl and Perl) (experience)
- Knowledge of synthesis, DFT, and backend-related methodologies and tools (experience)
- Strong communication skills are required, as you will interact with various groups (experience)
Responsibilities
- In this role, you will be responsible for developing and owning IP-level Netlist generation (Synthesis, UPF, scan insertion, external IP’s integration) & timing constraints, for both regular and custom requirements, from synthesis to sign-off, ensuring sign-off quality timing convergence. You will collaborate closely with the RTL designer to comprehend the design intent and clock structure, with the CAD team to understand and develop the flow, and with the Physical Design team to finalize and sign off on the timing. Additionally, you will actively contribute by generating ideas and plans to verify your own timing constraints. You will demonstrate innovation in timing constraints and flow to facilitate timing closure and address any potential pessimism or fallouts in timing analysis.
Tags & Categories