Timing Design Engineer
Apple
Timing Design Engineer
Job Description
Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something. As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- ASIC STAintermediate
- SoC designintermediate
- timing sign-offintermediate
- STA flow developmentintermediate
- timing constraintsintermediate
- RTL designintermediate
- clock structureintermediate
- CAD flow developmentintermediate
- Physical designintermediate
- timing closureintermediate
- timing analysisintermediate
Required Qualifications
- BS degree in technical discipline with minimum 3 years of relevant experience. (experience, 3 years)
Preferred Qualifications
- This position requires thorough knowledge of the ASIC design timing closure flow and methodology. (experience)
- The ideal candidate will have at least 2+ years of experience in writing ASIC timing constraints and timing closure (experience, 2 years)
- Epertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues (experience)
- Hands on experience in timing/SDC constraints generation and management, proficient in scripting languages (Tcl and Perl) (experience)
- Familiarity with synthesis, DFT and backend related methodology and tools. (experience)
- Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups. (experience)
Responsibilities
- As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
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Timing Design Engineer
Apple
Timing Design Engineer
Job Description
Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something. As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Locations
- Cupertino, California, United States 95014
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- ASIC STAintermediate
- SoC designintermediate
- timing sign-offintermediate
- STA flow developmentintermediate
- timing constraintsintermediate
- RTL designintermediate
- clock structureintermediate
- CAD flow developmentintermediate
- Physical designintermediate
- timing closureintermediate
- timing analysisintermediate
Required Qualifications
- BS degree in technical discipline with minimum 3 years of relevant experience. (experience, 3 years)
Preferred Qualifications
- This position requires thorough knowledge of the ASIC design timing closure flow and methodology. (experience)
- The ideal candidate will have at least 2+ years of experience in writing ASIC timing constraints and timing closure (experience, 2 years)
- Epertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues (experience)
- Hands on experience in timing/SDC constraints generation and management, proficient in scripting languages (Tcl and Perl) (experience)
- Familiarity with synthesis, DFT and backend related methodology and tools. (experience)
- Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups. (experience)
Responsibilities
- As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Tags & Categories
Answer 10 quick questions to check your fit for Timing Design Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs