Job Description

Locations

• San Diego, California, United States 92128
• Sunnyvale, California, United States 94085

Salary

Skills Required

• energy-efficient designintermediate
• RF/Analog engineeringintermediate
• Systems/PHY/MAC engineeringintermediate
• RTL designintermediate
• RTL integrationintermediate
• Emulationintermediate
• Verificationintermediate
• DFTintermediate
• Validationintermediate
• FW/SW engineeringintermediate
• SoC developmentintermediate
• custom hardware acceleratorsintermediate
• processor sub-systemsintermediate
• SoC architectureintermediate
• IP developmentintermediate
• ASIC designintermediate
• timing engineeringintermediate
• process improvementintermediate
• tool developmentintermediate
• multi-disciplinary collaborationintermediate
• design verificationintermediate

Required Qualifications

• Bachelors degree and 3+ years of relevant industry experience. (experience, 3 years)
• Timing constraint (SDC) creation at partition and chip level. (experience)
• Logic synthesis execution (verilog RTL to netlist). (experience)

Preferred Qualifications

• Strong knowledge of the entire ASIC design process, from RTL through synthesis, static timing analysis and place & route. (experience)
• Expertise in STA tools and flow. (experience)
• UPF usage for power and voltage islands. (experience)
• Knowledge of timing corners, operating modes, process variation and signal integrity-related issues. (experience)
• Skilled in scripting languages (TCL, PERL, Python), both standalone and within EDA tools. (experience)
• Proficient in the closure of end-to-end logic equivalence (FV, LEC) with functional ECOs in the mix. (experience)
• Familiarity with DFT approaches and constraints. (experience)
• Proficient with RTL Verilog/VHDL. (experience)
• Familiarity with digital top integration flows/methodology/checks. (experience)

Responsibilities

• As a Timing Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators and multiple processor sub-systems. There will be the opportunity to work closely with SoC architects and IP developers to develop SoCs that meet power, performance, and area goals for Apple’s products. You will help improve the processes, methods, and tools for designing and implementing these large, complex SoCs. Collaboration with multi-disciplinary groups will be needed to make sure designs are delivered on time and with the highest quality by incorporating targeted checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC creation effort, interfacing with all disciplines, with a critical impact in getting leading-edge products launched to delight millions of customers.
• Full chip and block-level timing constraint creation, review and closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).
• Execute low power physical synthesis techniques, deploying knowledge of UPF and power intent verification.
• Deploy and enhance methodology and flows related to timing constraint verification and timing closure.
• Generation of consistent block and full chip timing constraints.
• Support digital chip integration work and flows (e.g. CDC).
• Collaborate with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve first time Silicon success.
• Generally bridge between the RTL front end and place & route worlds.

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