Job Description

Locations

• San Francisco Bay Area, California, United States
• San Diego, California, United States 92128

Salary

Skills Required

• RTL verificationintermediate
• wireless MAC verificationintermediate
• test bench developmentintermediate
• verification environment developmentintermediate
• metric-driven verificationintermediate
• DV methodologyintermediate
• RF/Analog architecture and designintermediate
• Systems/PHY/MAC architecture and designintermediate
• VLSI/RTL design and integrationintermediate
• Design Verificationintermediate
• Emulationintermediate
• Test and Validationintermediate
• FW/SW engineeringintermediate

Required Qualifications

• Minimum requirement of a bachelors degree. (degree)

Preferred Qualifications

• Advanced knowledge of Verilog, SystemVerilog, and UVM. (experience)
• Knowledge of SystemVerilog Assertion. (experience)
• Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage. (experience)
• Proficient in shell and Python scripting, Perl scripting. (experience)
• Experience of using AI technologies in data mining/analysis. (experience)
• Verification experience of one or more of the following a plus: MAC, PHY, DMA, timer, AMBA bus and fabric, encryption/decryption engine. (experience)
• Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee. (experience)
• Should be a team player with excellent communication skills, self-motivated and well organized. (experience)

Responsibilities

• In this highly visible role, you will be at the center of a silicon design group with a critical impact on delivering world-class silicon to empower wireless products for hundreds of millions of customers. As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless MAC and its interfaces with the rest of the wireless SoC. You will interact with DV methodologists, designers, and communication systems engineers to develop reusable test bench and verification environment deploying the latest methodology with metric-driven verification, ensuring the highest design quality.
• Work closely with the system and design teams to review and understand the MAC subsystem microarchitecture, and create verification plan from specification, review and refine to achieve coverage targets.
• Build block level test benches, create UVM libraries, using the best-in-class DV methodology. Architect test benches with maximum reusability in mind.
• Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found.
• Create and analyze block/subsystem-level coverage models, and add test cases to increase coverage.
• Use machine learning and AI technologies to identify design and test bench issues and ensure DV quality.
• Support MAC subsystem validation using Palladium and/or FPGA.

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