Wireless SoC Design Engineer
Apple
Wireless SoC Design Engineer
Job Description
Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply. Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements. Engage in hardware/software partitioning discussions with software and firmware teams. Collaborate cross-functionally to ensure successful SoC integration, supporting design verification and validation across all phases—from concept to silicon bring-up. Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA) targets while ensuring design quality and maintainability.
Locations
- San Diego, California, United States 92128
- Sunnyvale, California, United States 94085
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- energy-efficient designintermediate
- RF/Analog architectureintermediate
- RF/Analog designintermediate
- Systems/PHY/MAC architectureintermediate
- Systems/PHY/MAC designintermediate
- VLSI/RTL designintermediate
- RTL integrationintermediate
- Emulationintermediate
- Design Verificationintermediate
- Test and Validationintermediate
- FW/SW engineeringintermediate
- microarchitecture developmentintermediate
- RTL developmentintermediate
- SoC IP designintermediate
- hardware/software partitioningintermediate
- cross-functional collaborationintermediate
- SoC integrationintermediate
- design verificationintermediate
- design validationintermediate
- silicon bring-upintermediate
- physical designintermediate
- DFTintermediate
- CADintermediate
- PPA optimizationintermediate
- design quality assuranceintermediate
- design maintainabilityintermediate
Required Qualifications
- BS and 10+ years of relevant industry experience. (experience, 10 years)
- Skilled in defining ASIC microarchitecture to meet functional requirements while managing performance, power, and area trade-offs. (experience)
- Knowledgeable about the ASIC design flow, including System Verilog RTL implementation, Lint, CDC, RDC, Synthesis and STA. (experience)
Preferred Qualifications
- Expertise in design domains such as memory subsystems, bus interfaces, CPU integration, DMA engines, Compression, Security IP design, and high-speed/low-speed peripherals like PCIE, QSPI, UART, and SPMI. (experience)
- Thorough understanding of cross clock-domain design principles and associated CDC requirements. (experience)
- Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis. (experience)
- Familiarity with ASIC test methodologies, encompassing DFT, scan insertion, memory BIST, and other related techniques. (experience)
- Strong communication skills, both written and oral. (experience)
Responsibilities
- Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements. Engage in hardware/software partitioning discussions with software and firmware teams. Collaborate cross-functionally to ensure successful SoC integration, supporting design verification and validation across all phases—from concept to silicon bring-up. Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA) targets while ensuring design quality and maintainability.
- Define microarchitecture working alongside architecture, software and firmware teams.
- Implement RTL that adheres to PPA requirements and Lint, CDC and RDC checks.
- Collaborate with Verification, DFT, Power, Physical design teams to delivery fully functional IP for SoC integration.
- Provide support for pre-silicon verification and software/firmware development.
- Assist in post-silicon validation, system integration and debugging effort.
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Answer 10 quick questions to check your fit for Wireless SoC Design Engineer @ Apple.
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Wireless SoC Design Engineer
Apple
Wireless SoC Design Engineer
Job Description
Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply. Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements. Engage in hardware/software partitioning discussions with software and firmware teams. Collaborate cross-functionally to ensure successful SoC integration, supporting design verification and validation across all phases—from concept to silicon bring-up. Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA) targets while ensuring design quality and maintainability.
Locations
- San Diego, California, United States 92128
- Sunnyvale, California, United States 94085
Salary
Estimated Salary Rangemedium confidence
25,000,000 - 60,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- energy-efficient designintermediate
- RF/Analog architectureintermediate
- RF/Analog designintermediate
- Systems/PHY/MAC architectureintermediate
- Systems/PHY/MAC designintermediate
- VLSI/RTL designintermediate
- RTL integrationintermediate
- Emulationintermediate
- Design Verificationintermediate
- Test and Validationintermediate
- FW/SW engineeringintermediate
- microarchitecture developmentintermediate
- RTL developmentintermediate
- SoC IP designintermediate
- hardware/software partitioningintermediate
- cross-functional collaborationintermediate
- SoC integrationintermediate
- design verificationintermediate
- design validationintermediate
- silicon bring-upintermediate
- physical designintermediate
- DFTintermediate
- CADintermediate
- PPA optimizationintermediate
- design quality assuranceintermediate
- design maintainabilityintermediate
Required Qualifications
- BS and 10+ years of relevant industry experience. (experience, 10 years)
- Skilled in defining ASIC microarchitecture to meet functional requirements while managing performance, power, and area trade-offs. (experience)
- Knowledgeable about the ASIC design flow, including System Verilog RTL implementation, Lint, CDC, RDC, Synthesis and STA. (experience)
Preferred Qualifications
- Expertise in design domains such as memory subsystems, bus interfaces, CPU integration, DMA engines, Compression, Security IP design, and high-speed/low-speed peripherals like PCIE, QSPI, UART, and SPMI. (experience)
- Thorough understanding of cross clock-domain design principles and associated CDC requirements. (experience)
- Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis. (experience)
- Familiarity with ASIC test methodologies, encompassing DFT, scan insertion, memory BIST, and other related techniques. (experience)
- Strong communication skills, both written and oral. (experience)
Responsibilities
- Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements. Engage in hardware/software partitioning discussions with software and firmware teams. Collaborate cross-functionally to ensure successful SoC integration, supporting design verification and validation across all phases—from concept to silicon bring-up. Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA) targets while ensuring design quality and maintainability.
- Define microarchitecture working alongside architecture, software and firmware teams.
- Implement RTL that adheres to PPA requirements and Lint, CDC and RDC checks.
- Collaborate with Verification, DFT, Power, Physical design teams to delivery fully functional IP for SoC integration.
- Provide support for pre-silicon verification and software/firmware development.
- Assist in post-silicon validation, system integration and debugging effort.
Tags & Categories
Answer 10 quick questions to check your fit for Wireless SoC Design Engineer @ Apple.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs