Job Description

Locations

• Sunnyvale, California, United States 94085

Salary

Skills Required

• UVM Testbenchesintermediate
• coverage driven test casesintermediate
• directed test casesintermediate
• AI toolsintermediate
• SOC verificationintermediate
• RTL verificationintermediate
• Wireless protocolsintermediate
• FW-HW interactionsintermediate
• multi-chip SOC debugintermediate
• high speed layered protocolsintermediate
• low-power driven architectureintermediate
• DV methodologyintermediate
• collaborationintermediate
• debate ideas openlyintermediate

Required Qualifications

• BS and a minimum of 10 years relevant industry experience. (experience, 10 years)
• Proven track record of working full ASIC cycle from concept to tape-out to bring-up, including test-planning, testbench implementation, test sequence creation and debugging, and coverage closure. (experience)
• Expertise in SystemVerilog coding and UVM methodology (experience)

Preferred Qualifications

• Dedicated/hands-on ASIC & SOC DV experience. (experience)
• Experience taping out large SOC systems with embedded processor cores. (experience)
• Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment. (experience)
• Experience with Formal Verification. (experience)
• In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification. (experience)
• Low Power Verification experience. (experience)
• Should be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges. (experience)

Responsibilities

• You will learn all aspects of a large-scale SOC, different types of SOC architectures, high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of multi-chip SOC debug architecture. As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state of the art Wireless SOCs. This position comes with responsibility for pre-silicon RTL verification of block and top-level SOC, all aspects of SOC Design Verification engineering, and will enable you to thrive in a dynamic multi-functional organization, debate ideas openly, and deliver on complex Wireless protocol chip requirements.
• Understand details of High Efficiency SOC Architecture, standard SOC peripherals such as PCIE, CPUs and multi-processor systems, Power Management and Low-Power schemes, DMA, DDR, PCIe, Memory Controller Subsystems, USB, PLL, power up, Secured Boot schemes.
• Deliver on Power Management designs using low-power methodologies and power up-down scenarios using UPF simulations.
• Create coverage driven verification plans from specifications, review and refine to achieve coverage targets.
• Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites to SOC level.
• Achieve targeted coverage, work with design, architecture, SW, FW and external IP delivery teams to efficiently integrate and verify overall SOC design.
• Work closely with DV methodology architects to improve verification metrics.

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