Role Overview

As a Static Timing Analysis (STA) Engineer at Arrow Electronics through eInfochips in San Jose, California, you'll dive deep into the heart of semiconductor innovation, ensuring that incoming Intellectual Property (IP) blocks meet the stringent timing requirements for cutting-edge AI applications. This role, stationed at our Cisco partner site, demands a timing expert who thrives on precision and possesses hands-on experience with industry-leading tools like Siemens Fractal and Crosscheck (formerly CrossFire, now Solido CrossCheck). Your mission is critical: validate Liberty (.lib) files, compare IP versions, and flag quality assurance issues that could derail silicon success.

Picture yourself as the gatekeeper for AI IP quality. You'll analyze various .lib views—setup, hold, recovery, removal—configuring sophisticated tools to differentiate true timing violations from benign discrepancies. With Arrow's vast ecosystem backing you, including partnerships with Qualcomm, NVIDIA, and others, you'll contribute to products deployed in 140 countries. This fully onsite role in San Jose offers immersion in a high-stakes environment where your expertise directly impacts multi-billion-dollar designs.

Day in the Life

Your day at Arrow Electronics in San Jose starts with a team huddle at the Cisco campus, reviewing overnight regression runs from IP validation suites. By 9:30 AM, you're deep into Siemens Fractal, scrutinizing timing arcs in a new AI accelerator IP. Lunch brings collaboration with design engineers, discussing hold violations flagged in Crosscheck reports.

Afternoon involves configuring IPdelta to compare rev1.2 against golden rev1.0, scripting TCL filters to suppress false positives. You'll run multi-corner analyses across PVT conditions, validating power-aware timing for low-power AI modes. Before EOD, you document findings in the IP sign-off portal, ensuring seamless handoff to physical design teams. Expect dynamic problem-solving, tool optimizations, and the thrill of catching subtle bugs that prevent costly respins.

Why San Jose, California?

San Jose, the epicenter of Silicon Valley in California, United States, pulses with innovation. Home to Cisco, Apple, and countless fabs, it's where semiconductor dreams become reality. Your Arrow office sits amid this tech mecca, offering proximity to world-class talent, networking events, and bleeding-edge projects. Beyond work, San Jose boasts mild Mediterranean climate, vibrant food scenes from Japantown to tapas bars, and outdoor escapes like Henry W. Coe State Park.

California's tech hub means unmatched career density—conferences, meetups, and headhunting opportunities abound. With average home prices reflecting its prestige, the lifestyle rewards include cultural festivals, professional sports (Sharks hockey), and easy drives to San Francisco or Santa Cruz beaches. For engineers, San Jose's ecosystem accelerates learning; you'll rub shoulders with PhDs pioneering 2nm nodes and AI hardware revolutions.

Career Growth Path

Arrow Electronics charts a clear trajectory for STA Engineers. Year 1 focuses on mastering IP validation flows, earning tool certifications. By Year 2, lead IP sign-off for major projects, mentoring juniors. Year 3-5: Transition to Senior STA Engineer or IP Methodology Lead, owning flows for 5nm+ processes.

Long-term, aim for Principal Engineer, STA Architect, or management tracks like Engineering Manager. eInfochips' growth—part of Arrow's $38B empire—fuels promotions; many advance to Director roles overseeing global teams. Tuition reimbursement supports MS/PhD pursuits, while internal mobility spans Qualcomm/NVIDIA partnerships. In San Jose, your skills command premium trajectories in AI, HPC, and automotive chips.

Compensation & Benefits

Arrow values your expertise with competitive pay estimated at $140,000-$190,000 annually for STA Engineers in San Jose, reflecting Silicon Valley standards and experience levels. This includes base salary, bonuses, and equity potential. Benefits shine: comprehensive medical/dental/vision, 401k matching up to 6%, HSA/HRA options, and generous PTO (20+ days vacation, unlimited sick).

Standouts include tuition reimbursement up to $5,250/year, disability coverage, life insurance, and wellness perks like gym stipends. Parental leave, ESPP, and flexible spending accounts round out a package rivaling FAANG. In high-cost San Jose, these offset living expenses while fueling growth.

Team & Culture

Join a collaborative, high-IQ team of 20+ engineers at the Cisco site, blending eInfochips veterans with Arrow's global network. Culture emphasizes innovation, work-life balance (no death marches), and inclusivity—Arrow's EEO policy ensures diversity thrives. Weekly tech shares, hackathons, and offsites build camaraderie.

Expect mentorship from 20+ year IC vets, flat hierarchies for idea flow, and tools like Splunk/Jira for efficiency. eInfochips' 'Sensor-to-Sunset' ethos means edge-to-cloud impact, fostering pride in 500+ products shipped worldwide. In San Jose, team lunches at top spots and volunteer days strengthen bonds.

How to Apply

Ready to shape AI silicon at Arrow? Submit your resume highlighting STA tool experience, .lib expertise, and IP validation projects. Include GitHub/TCL scripts if available. Our San Jose team reviews applications weekly; prompt submissions get priority. Interviews: technical screen (Crosscheck demo), IP case study, team fit chat. Background checks and Cisco badge process follow offers. Join 22,000 Arrow colleagues driving tomorrow's tech.

FAQ Section

Q: Is this role fully remote? No, it's fully onsite at Cisco in San Jose, California for collaboration.

Q: What tools must I know? Siemens Fractal/Crosscheck essential; IPdelta plus Liberty validation experience preferred.

Q: What's the experience level required? 5+ years in STA/IP validation for semiconductor design.

Q: Visa sponsorship available? Limited; US work authorization preferred.

Q: Typical project duration? Long-term, 1-3 years on Cisco AI programs.

Q: What's the team size? 20+ engineers focused on IP QA and timing.

Q: Benefits start date? Day 1 for full-time hires.

Q: Relocation assistance? Case-by-case for qualified candidates.

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