Analog Layout Engineer
Capgemini
Analog Layout Engineer
Job Description
Analog Layout Engineer
📋 Job Overview
The Analog Layout Engineer role at Capgemini involves working independently on block/IP level analog layout design from schematics, focusing on advanced FinFET technology nodes. Responsibilities include area estimation, floorplanning optimization, routing, and verifications with strong LVS/DRC debugging skills. The position supports innovative engineering services for leading organizations, emphasizing technical expertise and professional problem-solving.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Work independently on block/IP levels analog layout design from schematic
- Estimating the Area
- Optimizing Floorplan
- Routing and Verifications
- LVS/DRC debugging and other verifications for lower technology nodes like 5,7,10,14nm FinFET and below
✅ Required Qualifications
- Analog Layout Design (Block/IP level) - 4 to 10 Years
- LVS/DRC Debugging
- FinFET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below)
🛠️ Required Skills
- Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts
- EDA tools: Cadence Virtuoso Editor
- EDA tools: Calibre RVE
- Layout Optimization
- Area estimation
- Floorplanning
- Routing
- Good interpersonal skills
- Critical thinking abilities to resolve issues technically and professionally
🎁 Benefits & Perks
- Hybrid work options
- Adaptable schedules for healthy work-life balance
- Inclusive culture committed to growth, innovation, and excellence
- Continuous learning opportunities and certifications in emerging technologies like cloud and AI
Locations
- Bangalore, India
Salary
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel conceptsintermediate
- EDA tools: Cadence Virtuoso Editorintermediate
- EDA tools: Calibre RVEintermediate
- Layout Optimizationintermediate
- Area estimationintermediate
- Floorplanningintermediate
- Routingintermediate
- Good interpersonal skillsintermediate
- Critical thinking abilities to resolve issues technically and professionallyintermediate
Required Qualifications
- Analog Layout Design (Block/IP level) - 4 to 10 Years (experience)
- LVS/DRC Debugging (experience)
- FinFET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below) (experience)
Responsibilities
- Work independently on block/IP levels analog layout design from schematic
- Estimating the Area
- Optimizing Floorplan
- Routing and Verifications
- LVS/DRC debugging and other verifications for lower technology nodes like 5,7,10,14nm FinFET and below
Benefits
- general: Hybrid work options
- general: Adaptable schedules for healthy work-life balance
- general: Inclusive culture committed to growth, innovation, and excellence
- general: Continuous learning opportunities and certifications in emerging technologies like cloud and AI
Tags & Categories
Answer 10 quick questions to check your fit for Analog Layout Engineer @ Capgemini.
Related Books and Jobs
Analog Layout Engineer
Capgemini
Analog Layout Engineer
Job Description
Analog Layout Engineer
📋 Job Overview
The Analog Layout Engineer role at Capgemini involves working independently on block/IP level analog layout design from schematics, focusing on advanced FinFET technology nodes. Responsibilities include area estimation, floorplanning optimization, routing, and verifications with strong LVS/DRC debugging skills. The position supports innovative engineering services for leading organizations, emphasizing technical expertise and professional problem-solving.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Work independently on block/IP levels analog layout design from schematic
- Estimating the Area
- Optimizing Floorplan
- Routing and Verifications
- LVS/DRC debugging and other verifications for lower technology nodes like 5,7,10,14nm FinFET and below
✅ Required Qualifications
- Analog Layout Design (Block/IP level) - 4 to 10 Years
- LVS/DRC Debugging
- FinFET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below)
🛠️ Required Skills
- Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts
- EDA tools: Cadence Virtuoso Editor
- EDA tools: Calibre RVE
- Layout Optimization
- Area estimation
- Floorplanning
- Routing
- Good interpersonal skills
- Critical thinking abilities to resolve issues technically and professionally
🎁 Benefits & Perks
- Hybrid work options
- Adaptable schedules for healthy work-life balance
- Inclusive culture committed to growth, innovation, and excellence
- Continuous learning opportunities and certifications in emerging technologies like cloud and AI
Locations
- Bangalore, India
Salary
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel conceptsintermediate
- EDA tools: Cadence Virtuoso Editorintermediate
- EDA tools: Calibre RVEintermediate
- Layout Optimizationintermediate
- Area estimationintermediate
- Floorplanningintermediate
- Routingintermediate
- Good interpersonal skillsintermediate
- Critical thinking abilities to resolve issues technically and professionallyintermediate
Required Qualifications
- Analog Layout Design (Block/IP level) - 4 to 10 Years (experience)
- LVS/DRC Debugging (experience)
- FinFET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below) (experience)
Responsibilities
- Work independently on block/IP levels analog layout design from schematic
- Estimating the Area
- Optimizing Floorplan
- Routing and Verifications
- LVS/DRC debugging and other verifications for lower technology nodes like 5,7,10,14nm FinFET and below
Benefits
- general: Hybrid work options
- general: Adaptable schedules for healthy work-life balance
- general: Inclusive culture committed to growth, innovation, and excellence
- general: Continuous learning opportunities and certifications in emerging technologies like cloud and AI
Tags & Categories
Answer 10 quick questions to check your fit for Analog Layout Engineer @ Capgemini.
Related Books and Jobs