Analog Layout Engineer
Capgemini
Analog Layout Engineer
Job Description
Analog Layout Engineer
📋 Job Overview
The Analog Layout Engineer role at Capgemini Engineering involves independently executing block/IP-level analog layout design from schematics, focusing on advanced FinFET technology nodes. Responsibilities include area estimation, floorplan optimization, routing, and comprehensive verifications such as LVS/DRC debugging. The position requires strong technical expertise in physical design concepts and proficiency with EDA tools like Cadence Virtuoso Editor and Calibre RVE.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification
- Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below)
- Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects
- Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks
✅ Required Qualifications
- Bachelor's or Master's Degree
⭐ Preferred Qualifications
- Experience with advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below)
🛠️ Required Skills
- Analog Layout Design (Block/IP level)
- LVS/DRC Debugging
- FinFET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below)
- EDA Tools
- Cadence Virtuoso Editor
- Calibre RVE
- Layout Optimization
- Area estimation
- Floorplanning
- Routing
- Matching
- Electromigration (EM)
- Electrostatic Discharge (ESD)
- Latch-Up
- Shielding
- Parasitics
- Short Channel Effects
- Critical Thinking & Problem Solving
- Interpersonal and Communication Skills
- Team Collaboration
Locations
- Bangalore, India
Salary
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Analog Layout Design (Block/IP level)intermediate
- LVS/DRC Debuggingintermediate
- FinFET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below)intermediate
- EDA Toolsintermediate
- Cadence Virtuoso Editorintermediate
- Calibre RVEintermediate
- Layout Optimizationintermediate
- Area estimationintermediate
- Floorplanningintermediate
- Routingintermediate
- Matchingintermediate
- Electromigration (EM)intermediate
- Electrostatic Discharge (ESD)intermediate
- Latch-Upintermediate
- Shieldingintermediate
- Parasiticsintermediate
- Short Channel Effectsintermediate
- Critical Thinking & Problem Solvingintermediate
- Interpersonal and Communication Skillsintermediate
- Team Collaborationintermediate
Required Qualifications
- Bachelor's or Master's Degree (experience)
Preferred Qualifications
- Experience with advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below) (experience)
Responsibilities
- Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification
- Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below)
- Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects
- Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks
Tags & Categories
Answer 10 quick questions to check your fit for Analog Layout Engineer @ Capgemini.
Related Books and Jobs
Analog Layout Engineer
Capgemini
Analog Layout Engineer
Job Description
Analog Layout Engineer
📋 Job Overview
The Analog Layout Engineer role at Capgemini Engineering involves independently executing block/IP-level analog layout design from schematics, focusing on advanced FinFET technology nodes. Responsibilities include area estimation, floorplan optimization, routing, and comprehensive verifications such as LVS/DRC debugging. The position requires strong technical expertise in physical design concepts and proficiency with EDA tools like Cadence Virtuoso Editor and Calibre RVE.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification
- Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below)
- Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects
- Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks
✅ Required Qualifications
- Bachelor's or Master's Degree
⭐ Preferred Qualifications
- Experience with advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below)
🛠️ Required Skills
- Analog Layout Design (Block/IP level)
- LVS/DRC Debugging
- FinFET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below)
- EDA Tools
- Cadence Virtuoso Editor
- Calibre RVE
- Layout Optimization
- Area estimation
- Floorplanning
- Routing
- Matching
- Electromigration (EM)
- Electrostatic Discharge (ESD)
- Latch-Up
- Shielding
- Parasitics
- Short Channel Effects
- Critical Thinking & Problem Solving
- Interpersonal and Communication Skills
- Team Collaboration
Locations
- Bangalore, India
Salary
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Analog Layout Design (Block/IP level)intermediate
- LVS/DRC Debuggingintermediate
- FinFET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below)intermediate
- EDA Toolsintermediate
- Cadence Virtuoso Editorintermediate
- Calibre RVEintermediate
- Layout Optimizationintermediate
- Area estimationintermediate
- Floorplanningintermediate
- Routingintermediate
- Matchingintermediate
- Electromigration (EM)intermediate
- Electrostatic Discharge (ESD)intermediate
- Latch-Upintermediate
- Shieldingintermediate
- Parasiticsintermediate
- Short Channel Effectsintermediate
- Critical Thinking & Problem Solvingintermediate
- Interpersonal and Communication Skillsintermediate
- Team Collaborationintermediate
Required Qualifications
- Bachelor's or Master's Degree (experience)
Preferred Qualifications
- Experience with advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below) (experience)
Responsibilities
- Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification
- Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below)
- Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects
- Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks
Tags & Categories
Answer 10 quick questions to check your fit for Analog Layout Engineer @ Capgemini.
Related Books and Jobs