Design Verification Boost
Capgemini
Design Verification Boost
Job Description
Design Verification Boost
📋 Job Overview
The Design Verification Boost role at Capgemini involves leading a team of verification engineers to verify IPs and SoCs, ensuring first silicon success through coverage-driven methodologies. Responsibilities include defining verification strategies, writing test plans, and developing test benches and test cases using industry standards like UVM and SystemVerilog. The position emphasizes functional and code coverage, assertions, and experience with GLS, with a focus on AMS and power-aware verification.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Lead and manage a team of verification engineers
- Define strategies for verifying IPs and SoCs to ensure first silicon success
- Write test plans
- Develop test benches and test cases
- Use industry-standard methodologies (UVM/SystemVerilog)
- Focus on functional coverage, code coverage, and assertions
✅ Required Qualifications
- Manage and lead a team of Verification engineers
- Should have worked on GLS
- Proficiency in Verilog, SV, UVM/OVM
- IP Verification experience
- SoC Verification experience
⭐ Preferred Qualifications
- ARM based SoC verification experience
- Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts
- Emphasis on AMS and Power aware verification
🛠️ Required Skills
- Verilog
- SV (SystemVerilog)
- UVM/OVM
- IP Verification
- SoC Verification
- Scripting: Perl, Python, Shell, Tcl
- Test bench development
- Model development
- VIP development
- Functional coverage
- GLS
- LEC
- Emulation
- AMS
- ARM
- Protocols: AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR
- HVLs (Hardware Verification Languages)
- Assertions
- Code coverage
Locations
- Bangalore, India
Salary
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Verilogintermediate
- SV (SystemVerilog)intermediate
- UVM/OVMintermediate
- IP Verificationintermediate
- SoC Verificationintermediate
- Scripting: Perl, Python, Shell, Tclintermediate
- Test bench developmentintermediate
- Model developmentintermediate
- VIP developmentintermediate
- Functional coverageintermediate
- GLSintermediate
- LECintermediate
- Emulationintermediate
- AMSintermediate
- ARMintermediate
- Protocols: AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDRintermediate
- HVLs (Hardware Verification Languages)intermediate
- Assertionsintermediate
- Code coverageintermediate
Required Qualifications
- Manage and lead a team of Verification engineers (experience)
- Should have worked on GLS (experience)
- Proficiency in Verilog, SV, UVM/OVM (experience)
- IP Verification experience (experience)
- SoC Verification experience (experience)
Preferred Qualifications
- ARM based SoC verification experience (experience)
- Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts (experience)
- Emphasis on AMS and Power aware verification (experience)
Responsibilities
- Lead and manage a team of verification engineers
- Define strategies for verifying IPs and SoCs to ensure first silicon success
- Write test plans
- Develop test benches and test cases
- Use industry-standard methodologies (UVM/SystemVerilog)
- Focus on functional coverage, code coverage, and assertions
Tags & Categories
Design Verification Boost
Capgemini
Design Verification Boost
Job Description
Design Verification Boost
📋 Job Overview
The Design Verification Boost role at Capgemini involves leading a team of verification engineers to verify IPs and SoCs, ensuring first silicon success through coverage-driven methodologies. Responsibilities include defining verification strategies, writing test plans, and developing test benches and test cases using industry standards like UVM and SystemVerilog. The position emphasizes functional and code coverage, assertions, and experience with GLS, with a focus on AMS and power-aware verification.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Lead and manage a team of verification engineers
- Define strategies for verifying IPs and SoCs to ensure first silicon success
- Write test plans
- Develop test benches and test cases
- Use industry-standard methodologies (UVM/SystemVerilog)
- Focus on functional coverage, code coverage, and assertions
✅ Required Qualifications
- Manage and lead a team of Verification engineers
- Should have worked on GLS
- Proficiency in Verilog, SV, UVM/OVM
- IP Verification experience
- SoC Verification experience
⭐ Preferred Qualifications
- ARM based SoC verification experience
- Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts
- Emphasis on AMS and Power aware verification
🛠️ Required Skills
- Verilog
- SV (SystemVerilog)
- UVM/OVM
- IP Verification
- SoC Verification
- Scripting: Perl, Python, Shell, Tcl
- Test bench development
- Model development
- VIP development
- Functional coverage
- GLS
- LEC
- Emulation
- AMS
- ARM
- Protocols: AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR
- HVLs (Hardware Verification Languages)
- Assertions
- Code coverage
Locations
- Bangalore, India
Salary
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Verilogintermediate
- SV (SystemVerilog)intermediate
- UVM/OVMintermediate
- IP Verificationintermediate
- SoC Verificationintermediate
- Scripting: Perl, Python, Shell, Tclintermediate
- Test bench developmentintermediate
- Model developmentintermediate
- VIP developmentintermediate
- Functional coverageintermediate
- GLSintermediate
- LECintermediate
- Emulationintermediate
- AMSintermediate
- ARMintermediate
- Protocols: AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDRintermediate
- HVLs (Hardware Verification Languages)intermediate
- Assertionsintermediate
- Code coverageintermediate
Required Qualifications
- Manage and lead a team of Verification engineers (experience)
- Should have worked on GLS (experience)
- Proficiency in Verilog, SV, UVM/OVM (experience)
- IP Verification experience (experience)
- SoC Verification experience (experience)
Preferred Qualifications
- ARM based SoC verification experience (experience)
- Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts (experience)
- Emphasis on AMS and Power aware verification (experience)
Responsibilities
- Lead and manage a team of verification engineers
- Define strategies for verifying IPs and SoCs to ensure first silicon success
- Write test plans
- Develop test benches and test cases
- Use industry-standard methodologies (UVM/SystemVerilog)
- Focus on functional coverage, code coverage, and assertions
Tags & Categories