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GLS Verification Engineer

Capgemini

Engineering Jobs

GLS Verification Engineer

full-timePosted: Oct 28, 2025

Job Description

GLS Verification Engineer

📋 Job Overview

As a SoC GLS Verification Engineer at Capgemini Engineering, you will verify complex SoC designs using Gate-Level Simulation (GLS) techniques to ensure functional correctness, timing accuracy, and silicon quality. Collaborating with design and verification teams, you will debug issues, develop testbenches, and contribute to verification planning for high-performance SoCs. This role offers exposure to cutting-edge technologies in an innovative environment.

📍 Location: Bangalore

💼 Experience Level: Experienced Professionals

🏢 Business Unit: Engineering and RandD Services

🎯 Key Responsibilities

  • Perform GLS using Zero Delay, SDF, and Post-Layout GLS (PAGLS) techniques
  • Debug and resolve issues in gate-level simulations to ensure timing and functional correctness
  • Develop and maintain SystemVerilog/UVM testbenches for GLS environments
  • Collaborate with cross-functional teams to integrate and validate SoC components
  • Use tools like Synopsys Verdi and Cadence NC-Sim for simulation and waveform analysis
  • Contribute to verification planning, execution, and closure for SoC projects
  • Ensure alignment with SoC architecture and design specifications

✅ Required Qualifications

  • Total Experience: 5–7 years in SoC verification, with 3+ years of GLS-specific experience
  • Hands-on with Zero Delay, SDF, and PAGLS flows
  • Strong analytical and debugging capabilities in gate-level environments
  • Proficient in SystemVerilog, UVM, and testbench development
  • Experience with Synopsys Verdi, Cadence NC-Sim, and related tools
  • Solid grasp of SoC architecture, integration, and verification flows

🛠️ Required Skills

  • Gate-Level Simulation (GLS)
  • Zero Delay
  • SDF
  • Post-Layout GLS (PAGLS)
  • Debugging in gate-level environments
  • SystemVerilog
  • UVM
  • Testbench development
  • Synopsys Verdi
  • Cadence NC-Sim
  • SoC architecture
  • Integration
  • Verification flows
  • Analytical skills

🎁 Benefits & Perks

  • Exposure to cutting-edge SoC technologies and verification methodologies
  • Flexible work arrangements and a healthy work-life balance
  • A culture of continuous learning with access to training and certifications
  • Opportunities to work with industry experts and grow your technical expertise
  • Collaborative and innovation-driven environment

Locations

  • Bangalore, India

Salary

Estimated Salary Rangemedium confidence

2,500,000 - 4,200,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • Gate-Level Simulation (GLS)intermediate
  • Zero Delayintermediate
  • SDFintermediate
  • Post-Layout GLS (PAGLS)intermediate
  • Debugging in gate-level environmentsintermediate
  • SystemVerilogintermediate
  • UVMintermediate
  • Testbench developmentintermediate
  • Synopsys Verdiintermediate
  • Cadence NC-Simintermediate
  • SoC architectureintermediate
  • Integrationintermediate
  • Verification flowsintermediate
  • Analytical skillsintermediate

Required Qualifications

  • Total Experience: 5–7 years in SoC verification, with 3+ years of GLS-specific experience (experience)
  • Hands-on with Zero Delay, SDF, and PAGLS flows (experience)
  • Strong analytical and debugging capabilities in gate-level environments (experience)
  • Proficient in SystemVerilog, UVM, and testbench development (experience)
  • Experience with Synopsys Verdi, Cadence NC-Sim, and related tools (experience)
  • Solid grasp of SoC architecture, integration, and verification flows (experience)

Responsibilities

  • Perform GLS using Zero Delay, SDF, and Post-Layout GLS (PAGLS) techniques
  • Debug and resolve issues in gate-level simulations to ensure timing and functional correctness
  • Develop and maintain SystemVerilog/UVM testbenches for GLS environments
  • Collaborate with cross-functional teams to integrate and validate SoC components
  • Use tools like Synopsys Verdi and Cadence NC-Sim for simulation and waveform analysis
  • Contribute to verification planning, execution, and closure for SoC projects
  • Ensure alignment with SoC architecture and design specifications

Benefits

  • general: Exposure to cutting-edge SoC technologies and verification methodologies
  • general: Flexible work arrangements and a healthy work-life balance
  • general: A culture of continuous learning with access to training and certifications
  • general: Opportunities to work with industry experts and grow your technical expertise
  • general: Collaborative and innovation-driven environment

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Capgemini logo

GLS Verification Engineer

Capgemini

Engineering Jobs

GLS Verification Engineer

full-timePosted: Oct 28, 2025

Job Description

GLS Verification Engineer

📋 Job Overview

As a SoC GLS Verification Engineer at Capgemini Engineering, you will verify complex SoC designs using Gate-Level Simulation (GLS) techniques to ensure functional correctness, timing accuracy, and silicon quality. Collaborating with design and verification teams, you will debug issues, develop testbenches, and contribute to verification planning for high-performance SoCs. This role offers exposure to cutting-edge technologies in an innovative environment.

📍 Location: Bangalore

💼 Experience Level: Experienced Professionals

🏢 Business Unit: Engineering and RandD Services

🎯 Key Responsibilities

  • Perform GLS using Zero Delay, SDF, and Post-Layout GLS (PAGLS) techniques
  • Debug and resolve issues in gate-level simulations to ensure timing and functional correctness
  • Develop and maintain SystemVerilog/UVM testbenches for GLS environments
  • Collaborate with cross-functional teams to integrate and validate SoC components
  • Use tools like Synopsys Verdi and Cadence NC-Sim for simulation and waveform analysis
  • Contribute to verification planning, execution, and closure for SoC projects
  • Ensure alignment with SoC architecture and design specifications

✅ Required Qualifications

  • Total Experience: 5–7 years in SoC verification, with 3+ years of GLS-specific experience
  • Hands-on with Zero Delay, SDF, and PAGLS flows
  • Strong analytical and debugging capabilities in gate-level environments
  • Proficient in SystemVerilog, UVM, and testbench development
  • Experience with Synopsys Verdi, Cadence NC-Sim, and related tools
  • Solid grasp of SoC architecture, integration, and verification flows

🛠️ Required Skills

  • Gate-Level Simulation (GLS)
  • Zero Delay
  • SDF
  • Post-Layout GLS (PAGLS)
  • Debugging in gate-level environments
  • SystemVerilog
  • UVM
  • Testbench development
  • Synopsys Verdi
  • Cadence NC-Sim
  • SoC architecture
  • Integration
  • Verification flows
  • Analytical skills

🎁 Benefits & Perks

  • Exposure to cutting-edge SoC technologies and verification methodologies
  • Flexible work arrangements and a healthy work-life balance
  • A culture of continuous learning with access to training and certifications
  • Opportunities to work with industry experts and grow your technical expertise
  • Collaborative and innovation-driven environment

Locations

  • Bangalore, India

Salary

Estimated Salary Rangemedium confidence

2,500,000 - 4,200,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • Gate-Level Simulation (GLS)intermediate
  • Zero Delayintermediate
  • SDFintermediate
  • Post-Layout GLS (PAGLS)intermediate
  • Debugging in gate-level environmentsintermediate
  • SystemVerilogintermediate
  • UVMintermediate
  • Testbench developmentintermediate
  • Synopsys Verdiintermediate
  • Cadence NC-Simintermediate
  • SoC architectureintermediate
  • Integrationintermediate
  • Verification flowsintermediate
  • Analytical skillsintermediate

Required Qualifications

  • Total Experience: 5–7 years in SoC verification, with 3+ years of GLS-specific experience (experience)
  • Hands-on with Zero Delay, SDF, and PAGLS flows (experience)
  • Strong analytical and debugging capabilities in gate-level environments (experience)
  • Proficient in SystemVerilog, UVM, and testbench development (experience)
  • Experience with Synopsys Verdi, Cadence NC-Sim, and related tools (experience)
  • Solid grasp of SoC architecture, integration, and verification flows (experience)

Responsibilities

  • Perform GLS using Zero Delay, SDF, and Post-Layout GLS (PAGLS) techniques
  • Debug and resolve issues in gate-level simulations to ensure timing and functional correctness
  • Develop and maintain SystemVerilog/UVM testbenches for GLS environments
  • Collaborate with cross-functional teams to integrate and validate SoC components
  • Use tools like Synopsys Verdi and Cadence NC-Sim for simulation and waveform analysis
  • Contribute to verification planning, execution, and closure for SoC projects
  • Ensure alignment with SoC architecture and design specifications

Benefits

  • general: Exposure to cutting-edge SoC technologies and verification methodologies
  • general: Flexible work arrangements and a healthy work-life balance
  • general: A culture of continuous learning with access to training and certifications
  • general: Opportunities to work with industry experts and grow your technical expertise
  • general: Collaborative and innovation-driven environment

Target Your Resume for "GLS Verification Engineer" , Capgemini

Get personalized recommendations to optimize your resume specifically for GLS Verification Engineer. Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "GLS Verification Engineer" , Capgemini

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Tags & Categories

Engineering and RandD ServicesProducts & Systems EngineeringExperienced ProfessionalsEngineering and RandD Services

Answer 10 quick questions to check your fit for GLS Verification Engineer @ Capgemini.

Quiz Challenge
10 Questions
~2 Minutes
Instant Score

Related Books and Jobs

No related jobs found at the moment.