Memory Circuit Engineer
Capgemini
Memory Circuit Engineer
Job Description
Memory Circuit Engineer
📋 Job Overview
The Memory Circuit Engineer role at Capgemini involves designing and verifying memory circuits for semiconductor applications in the electrical, electronics, and semiconductor domains. Engineers will focus on full custom circuit design, bitcell development, and analysis of memory blocks, while contributing to innovative architectures and providing guidance to teams. This position offers opportunities to work independently on client needs, solve problems, and collaborate in a dynamic R&D environment.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Develops competency in own area of expertise in Electrical, Electronics and Semiconductor
- Shares expertise and provides guidance and support to others
- Interprets clients needs
- Completes own role independently or with minimum supervision
- Identifies problems and relevant issues in straightforward situations and generates solutions
- Contributes in teamwork and interacts with customers
✅ Required Qualifications
- Minimum 4 to 12 Years of experience In Memory Circuit Design
- Digital Full Custom CKT Design
- Bitcell Design
- Design of simpler memory blocks (decoding, rowdec, SA, IO block w/o RA, WA)
- Design of complex blocks like RA, WA, Rd selftime and write selftime
- SPRAM/Dual Port/ROM architecture
- Library CKT verification at Compiler level
- Sense Amp Analysis (offset, pulse width, glitch, coupling etc.)
- Read/Write Selftime Analysis
- Functional/Power Marginality analysis
- Latch analysis
- Power ON and power sequencing checks
- Library CKT Char and Char verification
- Timing, power, leak etc. setups (definitions, stimuli, MCF etc.)
- Timing, power, leak etc. verification
- LVF analysis and implementation
- Critical Path Tight Stimuli (CPTS)
- Full Cut Tight Stimuli (FCTS)
- FC power, timing, power, leak and comparison with CP
- Decoupling CAP
- Ageing (char)
- Concept of Grid
- Infrastructure, Packaging & Delivery
⭐ Preferred Qualifications
- Exploring and providing new ckt design and memory architectures
- Extraction, IR/EM analysis, PERC etc.
🛠️ Required Skills
- Memory Circuit Design
- Digital Full Custom CKT Design
- Bitcell Design
- Decoding
- Rowdec
- Sense Amp (SA)
- IO block
- Read Address (RA)
- Write Address (WA)
- Read selftime
- Write selftime
- SPRAM
- Dual Port
- ROM architecture
- Library CKT verification at Compiler level
- Sense Amp Analysis (offset, pulse width, glitch, coupling)
- Read/Write Selftime Analysis
- Functional/Power Marginality analysis
- Latch analysis
- ESPCV
- Power ON and power sequencing checks
- Extraction
- IR/EM analysis
- PERC
- Library CKT Char and Char verification
- Timing setups
- Power setups
- Leak setups
- Definitions
- Stimuli
- MCF
- Timing verification
- Power verification
- Leak verification
- LVF analysis
- LVF implementation
- Critical Path Tight Stimuli (CPTS)
- Full Cut Tight Stimuli (FCTS)
- FC power
- FC timing
- FC leak
- Comparison with CP
- Decoupling CAP
- Ageing (char)
- Concept of Grid
- Infrastructure
- Packaging
- Delivery
- ST Methodology
- CAD Tools
- Global BIST solutions (MASIS)
- IR Drop solutions
- AVM
- RedHawk
- Simulators (XA)
- Simulators (Eldo)
- High sigma analysis (eldo FFP)
🎁 Benefits & Perks
- Hybrid work options
- Adaptable schedules to maintain a healthy work-life balance
- Inclusive culture committed to growth, innovation, and excellence
- Continuous learning opportunities
- Certifications in emerging technologies like cloud and AI
Locations
- Bangalore, India
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Memory Circuit Designintermediate
- Digital Full Custom CKT Designintermediate
- Bitcell Designintermediate
- Decodingintermediate
- Rowdecintermediate
- Sense Amp (SA)intermediate
- IO blockintermediate
- Read Address (RA)intermediate
- Write Address (WA)intermediate
- Read selftimeintermediate
- Write selftimeintermediate
- SPRAMintermediate
- Dual Portintermediate
- ROM architectureintermediate
- Library CKT verification at Compiler levelintermediate
- Sense Amp Analysis (offset, pulse width, glitch, coupling)intermediate
- Read/Write Selftime Analysisintermediate
- Functional/Power Marginality analysisintermediate
- Latch analysisintermediate
- ESPCVintermediate
- Power ON and power sequencing checksintermediate
- Extractionintermediate
- IR/EM analysisintermediate
- PERCintermediate
- Library CKT Char and Char verificationintermediate
- Timing setupsintermediate
- Power setupsintermediate
- Leak setupsintermediate
- Definitionsintermediate
- Stimuliintermediate
- MCFintermediate
- Timing verificationintermediate
- Power verificationintermediate
- Leak verificationintermediate
- LVF analysisintermediate
- LVF implementationintermediate
- Critical Path Tight Stimuli (CPTS)intermediate
- Full Cut Tight Stimuli (FCTS)intermediate
- FC powerintermediate
- FC timingintermediate
- FC leakintermediate
- Comparison with CPintermediate
- Decoupling CAPintermediate
- Ageing (char)intermediate
- Concept of Gridintermediate
- Infrastructureintermediate
- Packagingintermediate
- Deliveryintermediate
- ST Methodologyintermediate
- CAD Toolsintermediate
- Global BIST solutions (MASIS)intermediate
- IR Drop solutionsintermediate
- AVMintermediate
- RedHawkintermediate
- Simulators (XA)intermediate
- Simulators (Eldo)intermediate
- High sigma analysis (eldo FFP)intermediate
Required Qualifications
- Minimum 4 to 12 Years of experience In Memory Circuit Design (experience)
- Digital Full Custom CKT Design (experience)
- Bitcell Design (experience)
- Design of simpler memory blocks (decoding, rowdec, SA, IO block w/o RA, WA) (experience)
- Design of complex blocks like RA, WA, Rd selftime and write selftime (experience)
- SPRAM/Dual Port/ROM architecture (experience)
- Library CKT verification at Compiler level (experience)
- Sense Amp Analysis (offset, pulse width, glitch, coupling etc.) (experience)
- Read/Write Selftime Analysis (experience)
- Functional/Power Marginality analysis (experience)
- Latch analysis (experience)
- Power ON and power sequencing checks (experience)
- Library CKT Char and Char verification (experience)
- Timing, power, leak etc. setups (definitions, stimuli, MCF etc.) (experience)
- Timing, power, leak etc. verification (experience)
- LVF analysis and implementation (experience)
- Critical Path Tight Stimuli (CPTS) (experience)
- Full Cut Tight Stimuli (FCTS) (experience)
- FC power, timing, power, leak and comparison with CP (experience)
- Decoupling CAP (experience)
- Ageing (char) (experience)
- Concept of Grid (experience)
- Infrastructure, Packaging & Delivery (experience)
Preferred Qualifications
- Exploring and providing new ckt design and memory architectures (experience)
- Extraction, IR/EM analysis, PERC etc. (experience)
Responsibilities
- Develops competency in own area of expertise in Electrical, Electronics and Semiconductor
- Shares expertise and provides guidance and support to others
- Interprets clients needs
- Completes own role independently or with minimum supervision
- Identifies problems and relevant issues in straightforward situations and generates solutions
- Contributes in teamwork and interacts with customers
Benefits
- general: Hybrid work options
- general: Adaptable schedules to maintain a healthy work-life balance
- general: Inclusive culture committed to growth, innovation, and excellence
- general: Continuous learning opportunities
- general: Certifications in emerging technologies like cloud and AI
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Answer 10 quick questions to check your fit for Memory Circuit Engineer @ Capgemini.
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Memory Circuit Engineer
Capgemini
Memory Circuit Engineer
Job Description
Memory Circuit Engineer
📋 Job Overview
The Memory Circuit Engineer role at Capgemini involves designing and verifying memory circuits for semiconductor applications in the electrical, electronics, and semiconductor domains. Engineers will focus on full custom circuit design, bitcell development, and analysis of memory blocks, while contributing to innovative architectures and providing guidance to teams. This position offers opportunities to work independently on client needs, solve problems, and collaborate in a dynamic R&D environment.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Develops competency in own area of expertise in Electrical, Electronics and Semiconductor
- Shares expertise and provides guidance and support to others
- Interprets clients needs
- Completes own role independently or with minimum supervision
- Identifies problems and relevant issues in straightforward situations and generates solutions
- Contributes in teamwork and interacts with customers
✅ Required Qualifications
- Minimum 4 to 12 Years of experience In Memory Circuit Design
- Digital Full Custom CKT Design
- Bitcell Design
- Design of simpler memory blocks (decoding, rowdec, SA, IO block w/o RA, WA)
- Design of complex blocks like RA, WA, Rd selftime and write selftime
- SPRAM/Dual Port/ROM architecture
- Library CKT verification at Compiler level
- Sense Amp Analysis (offset, pulse width, glitch, coupling etc.)
- Read/Write Selftime Analysis
- Functional/Power Marginality analysis
- Latch analysis
- Power ON and power sequencing checks
- Library CKT Char and Char verification
- Timing, power, leak etc. setups (definitions, stimuli, MCF etc.)
- Timing, power, leak etc. verification
- LVF analysis and implementation
- Critical Path Tight Stimuli (CPTS)
- Full Cut Tight Stimuli (FCTS)
- FC power, timing, power, leak and comparison with CP
- Decoupling CAP
- Ageing (char)
- Concept of Grid
- Infrastructure, Packaging & Delivery
⭐ Preferred Qualifications
- Exploring and providing new ckt design and memory architectures
- Extraction, IR/EM analysis, PERC etc.
🛠️ Required Skills
- Memory Circuit Design
- Digital Full Custom CKT Design
- Bitcell Design
- Decoding
- Rowdec
- Sense Amp (SA)
- IO block
- Read Address (RA)
- Write Address (WA)
- Read selftime
- Write selftime
- SPRAM
- Dual Port
- ROM architecture
- Library CKT verification at Compiler level
- Sense Amp Analysis (offset, pulse width, glitch, coupling)
- Read/Write Selftime Analysis
- Functional/Power Marginality analysis
- Latch analysis
- ESPCV
- Power ON and power sequencing checks
- Extraction
- IR/EM analysis
- PERC
- Library CKT Char and Char verification
- Timing setups
- Power setups
- Leak setups
- Definitions
- Stimuli
- MCF
- Timing verification
- Power verification
- Leak verification
- LVF analysis
- LVF implementation
- Critical Path Tight Stimuli (CPTS)
- Full Cut Tight Stimuli (FCTS)
- FC power
- FC timing
- FC leak
- Comparison with CP
- Decoupling CAP
- Ageing (char)
- Concept of Grid
- Infrastructure
- Packaging
- Delivery
- ST Methodology
- CAD Tools
- Global BIST solutions (MASIS)
- IR Drop solutions
- AVM
- RedHawk
- Simulators (XA)
- Simulators (Eldo)
- High sigma analysis (eldo FFP)
🎁 Benefits & Perks
- Hybrid work options
- Adaptable schedules to maintain a healthy work-life balance
- Inclusive culture committed to growth, innovation, and excellence
- Continuous learning opportunities
- Certifications in emerging technologies like cloud and AI
Locations
- Bangalore, India
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Memory Circuit Designintermediate
- Digital Full Custom CKT Designintermediate
- Bitcell Designintermediate
- Decodingintermediate
- Rowdecintermediate
- Sense Amp (SA)intermediate
- IO blockintermediate
- Read Address (RA)intermediate
- Write Address (WA)intermediate
- Read selftimeintermediate
- Write selftimeintermediate
- SPRAMintermediate
- Dual Portintermediate
- ROM architectureintermediate
- Library CKT verification at Compiler levelintermediate
- Sense Amp Analysis (offset, pulse width, glitch, coupling)intermediate
- Read/Write Selftime Analysisintermediate
- Functional/Power Marginality analysisintermediate
- Latch analysisintermediate
- ESPCVintermediate
- Power ON and power sequencing checksintermediate
- Extractionintermediate
- IR/EM analysisintermediate
- PERCintermediate
- Library CKT Char and Char verificationintermediate
- Timing setupsintermediate
- Power setupsintermediate
- Leak setupsintermediate
- Definitionsintermediate
- Stimuliintermediate
- MCFintermediate
- Timing verificationintermediate
- Power verificationintermediate
- Leak verificationintermediate
- LVF analysisintermediate
- LVF implementationintermediate
- Critical Path Tight Stimuli (CPTS)intermediate
- Full Cut Tight Stimuli (FCTS)intermediate
- FC powerintermediate
- FC timingintermediate
- FC leakintermediate
- Comparison with CPintermediate
- Decoupling CAPintermediate
- Ageing (char)intermediate
- Concept of Gridintermediate
- Infrastructureintermediate
- Packagingintermediate
- Deliveryintermediate
- ST Methodologyintermediate
- CAD Toolsintermediate
- Global BIST solutions (MASIS)intermediate
- IR Drop solutionsintermediate
- AVMintermediate
- RedHawkintermediate
- Simulators (XA)intermediate
- Simulators (Eldo)intermediate
- High sigma analysis (eldo FFP)intermediate
Required Qualifications
- Minimum 4 to 12 Years of experience In Memory Circuit Design (experience)
- Digital Full Custom CKT Design (experience)
- Bitcell Design (experience)
- Design of simpler memory blocks (decoding, rowdec, SA, IO block w/o RA, WA) (experience)
- Design of complex blocks like RA, WA, Rd selftime and write selftime (experience)
- SPRAM/Dual Port/ROM architecture (experience)
- Library CKT verification at Compiler level (experience)
- Sense Amp Analysis (offset, pulse width, glitch, coupling etc.) (experience)
- Read/Write Selftime Analysis (experience)
- Functional/Power Marginality analysis (experience)
- Latch analysis (experience)
- Power ON and power sequencing checks (experience)
- Library CKT Char and Char verification (experience)
- Timing, power, leak etc. setups (definitions, stimuli, MCF etc.) (experience)
- Timing, power, leak etc. verification (experience)
- LVF analysis and implementation (experience)
- Critical Path Tight Stimuli (CPTS) (experience)
- Full Cut Tight Stimuli (FCTS) (experience)
- FC power, timing, power, leak and comparison with CP (experience)
- Decoupling CAP (experience)
- Ageing (char) (experience)
- Concept of Grid (experience)
- Infrastructure, Packaging & Delivery (experience)
Preferred Qualifications
- Exploring and providing new ckt design and memory architectures (experience)
- Extraction, IR/EM analysis, PERC etc. (experience)
Responsibilities
- Develops competency in own area of expertise in Electrical, Electronics and Semiconductor
- Shares expertise and provides guidance and support to others
- Interprets clients needs
- Completes own role independently or with minimum supervision
- Identifies problems and relevant issues in straightforward situations and generates solutions
- Contributes in teamwork and interacts with customers
Benefits
- general: Hybrid work options
- general: Adaptable schedules to maintain a healthy work-life balance
- general: Inclusive culture committed to growth, innovation, and excellence
- general: Continuous learning opportunities
- general: Certifications in emerging technologies like cloud and AI
Tags & Categories
Answer 10 quick questions to check your fit for Memory Circuit Engineer @ Capgemini.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs