Memory Layout Engineer
Capgemini
Memory Layout Engineer
Job Description
Memory Layout Engineer
📋 Job Overview
As a Memory/Custom Layout Design Engineer at Capgemini Engineering, you will design high-performance memory leafcell layout libraries from scratch and integrate them at the top level using advanced FinFET technologies. The role focuses on optimizing layouts for performance, reliability, and manufacturability while performing physical verification and analysis. You will collaborate in a cutting-edge team to support innovative semiconductor projects across industries.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Design memory leafcell layout libraries from scratch, including top-level integration
- Apply knowledge of various memory architectures to layout design
- Optimize layout for performance, area, and reliability
- Work with FinFET technology, understanding DRC limitations and layout constraints
- Perform physical verification and debug issues related to DRC, LVS, ERC, and boundary conditions
- Run and fix issues related to EM and IR analysis
- Use Cadence Virtuoso for layout editing and Calibre for physical verification
✅ Required Qualifications
- 4–10 years of experience in Memory or Custom Layout Design
- Strong understanding of memory architectures and layout optimization techniques
- Hands-on experience with FinFET technology and DRC rules
- Proficient in physical verification flows (DRC, LVS, ERC) and debugging
- Experience with EM/IR analysis and fixes
- Skilled in Cadence Virtuoso and Calibre tools
- Familiarity with scripting languages for automation and flow customization
- Bachelor’s degree (B.E/B.Tech) in Engineering or related field
🛠️ Required Skills
- Memory architectures
- Layout optimization techniques
- FinFET technology
- DRC rules
- Physical verification flows (DRC, LVS, ERC)
- Debugging
- EM/IR analysis
- Cadence Virtuoso
- Calibre tools
- Scripting languages for automation and flow customization
🎁 Benefits & Perks
- Collaborative environment
- Opportunities for technical growth
- Exposure to industry-leading tools and methodologies
- Culture that supports innovation, learning, and excellence
Locations
- Bangalore, India
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Memory architecturesintermediate
- Layout optimization techniquesintermediate
- FinFET technologyintermediate
- DRC rulesintermediate
- Physical verification flows (DRC, LVS, ERC)intermediate
- Debuggingintermediate
- EM/IR analysisintermediate
- Cadence Virtuosointermediate
- Calibre toolsintermediate
- Scripting languages for automation and flow customizationintermediate
Required Qualifications
- 4–10 years of experience in Memory or Custom Layout Design (experience)
- Strong understanding of memory architectures and layout optimization techniques (experience)
- Hands-on experience with FinFET technology and DRC rules (experience)
- Proficient in physical verification flows (DRC, LVS, ERC) and debugging (experience)
- Experience with EM/IR analysis and fixes (experience)
- Skilled in Cadence Virtuoso and Calibre tools (experience)
- Familiarity with scripting languages for automation and flow customization (experience)
- Bachelor’s degree (B.E/B.Tech) in Engineering or related field (experience)
Responsibilities
- Design memory leafcell layout libraries from scratch, including top-level integration
- Apply knowledge of various memory architectures to layout design
- Optimize layout for performance, area, and reliability
- Work with FinFET technology, understanding DRC limitations and layout constraints
- Perform physical verification and debug issues related to DRC, LVS, ERC, and boundary conditions
- Run and fix issues related to EM and IR analysis
- Use Cadence Virtuoso for layout editing and Calibre for physical verification
Benefits
- general: Collaborative environment
- general: Opportunities for technical growth
- general: Exposure to industry-leading tools and methodologies
- general: Culture that supports innovation, learning, and excellence
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Answer 10 quick questions to check your fit for Memory Layout Engineer @ Capgemini.
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Memory Layout Engineer
Capgemini
Memory Layout Engineer
Job Description
Memory Layout Engineer
📋 Job Overview
As a Memory/Custom Layout Design Engineer at Capgemini Engineering, you will design high-performance memory leafcell layout libraries from scratch and integrate them at the top level using advanced FinFET technologies. The role focuses on optimizing layouts for performance, reliability, and manufacturability while performing physical verification and analysis. You will collaborate in a cutting-edge team to support innovative semiconductor projects across industries.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Design memory leafcell layout libraries from scratch, including top-level integration
- Apply knowledge of various memory architectures to layout design
- Optimize layout for performance, area, and reliability
- Work with FinFET technology, understanding DRC limitations and layout constraints
- Perform physical verification and debug issues related to DRC, LVS, ERC, and boundary conditions
- Run and fix issues related to EM and IR analysis
- Use Cadence Virtuoso for layout editing and Calibre for physical verification
✅ Required Qualifications
- 4–10 years of experience in Memory or Custom Layout Design
- Strong understanding of memory architectures and layout optimization techniques
- Hands-on experience with FinFET technology and DRC rules
- Proficient in physical verification flows (DRC, LVS, ERC) and debugging
- Experience with EM/IR analysis and fixes
- Skilled in Cadence Virtuoso and Calibre tools
- Familiarity with scripting languages for automation and flow customization
- Bachelor’s degree (B.E/B.Tech) in Engineering or related field
🛠️ Required Skills
- Memory architectures
- Layout optimization techniques
- FinFET technology
- DRC rules
- Physical verification flows (DRC, LVS, ERC)
- Debugging
- EM/IR analysis
- Cadence Virtuoso
- Calibre tools
- Scripting languages for automation and flow customization
🎁 Benefits & Perks
- Collaborative environment
- Opportunities for technical growth
- Exposure to industry-leading tools and methodologies
- Culture that supports innovation, learning, and excellence
Locations
- Bangalore, India
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Memory architecturesintermediate
- Layout optimization techniquesintermediate
- FinFET technologyintermediate
- DRC rulesintermediate
- Physical verification flows (DRC, LVS, ERC)intermediate
- Debuggingintermediate
- EM/IR analysisintermediate
- Cadence Virtuosointermediate
- Calibre toolsintermediate
- Scripting languages for automation and flow customizationintermediate
Required Qualifications
- 4–10 years of experience in Memory or Custom Layout Design (experience)
- Strong understanding of memory architectures and layout optimization techniques (experience)
- Hands-on experience with FinFET technology and DRC rules (experience)
- Proficient in physical verification flows (DRC, LVS, ERC) and debugging (experience)
- Experience with EM/IR analysis and fixes (experience)
- Skilled in Cadence Virtuoso and Calibre tools (experience)
- Familiarity with scripting languages for automation and flow customization (experience)
- Bachelor’s degree (B.E/B.Tech) in Engineering or related field (experience)
Responsibilities
- Design memory leafcell layout libraries from scratch, including top-level integration
- Apply knowledge of various memory architectures to layout design
- Optimize layout for performance, area, and reliability
- Work with FinFET technology, understanding DRC limitations and layout constraints
- Perform physical verification and debug issues related to DRC, LVS, ERC, and boundary conditions
- Run and fix issues related to EM and IR analysis
- Use Cadence Virtuoso for layout editing and Calibre for physical verification
Benefits
- general: Collaborative environment
- general: Opportunities for technical growth
- general: Exposure to industry-leading tools and methodologies
- general: Culture that supports innovation, learning, and excellence
Tags & Categories
Answer 10 quick questions to check your fit for Memory Layout Engineer @ Capgemini.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs