Signal Integrity and Power Integrity Engineer
Capgemini
Signal Integrity and Power Integrity Engineer
Job Description
Signal Integrity and Power Integrity Engineer
📋 Job Overview
As a Signal Integrity and Power Integrity Engineer at Capgemini, you will perform high-speed SI/PI simulations and testing for advanced interfaces and platforms. You will collaborate with design and layout teams to optimize signal performance and reliability in complex hardware systems. The role involves analysis, validation, and root cause resolution to ensure robust system design.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Perform pre- and post-layout SI/PI analysis for die, package, and board-level designs
- Conduct simulations using IBIS/IBIS-AMI models and analyze eye diagrams to recommend equalization settings
- Analyze S-parameters including insertion loss, return loss, crosstalk, and TDR
- Provide layout constraints and recommendations to ensure signal integrity
- Select appropriate stack-up materials including dielectric, copper thickness, and impedance control
- Work with high-speed interfaces such as PCIe Gen3/4/5, DDR4/5, LPDDR4/5, 10G Ethernet, and USB 3.2 Gen1/2
- Utilize tools like oscilloscopes and VNAs for hardware validation and debugging
- Identify technical issues and perform root cause analysis for effective resolution
✅ Required Qualifications
- Bachelor’s or Master’s degree in Engineering (BE/B.Tech/M.E/M.Tech or equivalent)
- 7–10 years of experience in high-speed SI/PI simulations and testing
- Strong expertise in interfaces such as PCIe, DDR, LPDDR, Ethernet, and USB
- Hands-on experience with IBIS/IBIS-AMI models and eye diagram analysis
- Proficient in S-parameter analysis and signal integrity metrics
- Knowledge of stack-up design including dielectric selection and impedance control
- Experience providing layout constraints and collaborating with design teams
⭐ Preferred Qualifications
- Experience with oscilloscopes, VNAs, and hardware debugging tools
🛠️ Required Skills
- Signal Integrity (SI) simulations
- Power Integrity (PI) simulations
- IBIS/IBIS-AMI models
- Eye diagram analysis
- Equalization settings
- S-parameter analysis
- Insertion loss
- Return loss
- Crosstalk
- TDR (Time Domain Reflectometry)
- Layout constraints
- Stack-up design
- Dielectric selection
- Copper thickness
- Impedance control
- High-speed interfaces: PCIe Gen3/4/5, DDR4/5, LPDDR4/5, 10G Ethernet, USB 3.2 Gen1/2
- Oscilloscopes
- VNAs (Vector Network Analyzers)
- Hardware validation and debugging
- Root cause analysis
- Collaboration with design and layout teams
🎁 Benefits & Perks
- Remote work options
- Adaptable schedules for work-life balance
- Inclusive culture focused on growth, innovation, and excellence
- Continuous learning opportunities
- Certifications in emerging technologies like cloud and AI
Locations
- Bangalore, India
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Signal Integrity (SI) simulationsintermediate
- Power Integrity (PI) simulationsintermediate
- IBIS/IBIS-AMI modelsintermediate
- Eye diagram analysisintermediate
- Equalization settingsintermediate
- S-parameter analysisintermediate
- Insertion lossintermediate
- Return lossintermediate
- Crosstalkintermediate
- TDR (Time Domain Reflectometry)intermediate
- Layout constraintsintermediate
- Stack-up designintermediate
- Dielectric selectionintermediate
- Copper thicknessintermediate
- Impedance controlintermediate
- High-speed interfaces: PCIe Gen3/4/5, DDR4/5, LPDDR4/5, 10G Ethernet, USB 3.2 Gen1/2intermediate
- Oscilloscopesintermediate
- VNAs (Vector Network Analyzers)intermediate
- Hardware validation and debuggingintermediate
- Root cause analysisintermediate
- Collaboration with design and layout teamsintermediate
Required Qualifications
- Bachelor’s or Master’s degree in Engineering (BE/B.Tech/M.E/M.Tech or equivalent) (experience)
- 7–10 years of experience in high-speed SI/PI simulations and testing (experience)
- Strong expertise in interfaces such as PCIe, DDR, LPDDR, Ethernet, and USB (experience)
- Hands-on experience with IBIS/IBIS-AMI models and eye diagram analysis (experience)
- Proficient in S-parameter analysis and signal integrity metrics (experience)
- Knowledge of stack-up design including dielectric selection and impedance control (experience)
- Experience providing layout constraints and collaborating with design teams (experience)
Preferred Qualifications
- Experience with oscilloscopes, VNAs, and hardware debugging tools (experience)
Responsibilities
- Perform pre- and post-layout SI/PI analysis for die, package, and board-level designs
- Conduct simulations using IBIS/IBIS-AMI models and analyze eye diagrams to recommend equalization settings
- Analyze S-parameters including insertion loss, return loss, crosstalk, and TDR
- Provide layout constraints and recommendations to ensure signal integrity
- Select appropriate stack-up materials including dielectric, copper thickness, and impedance control
- Work with high-speed interfaces such as PCIe Gen3/4/5, DDR4/5, LPDDR4/5, 10G Ethernet, and USB 3.2 Gen1/2
- Utilize tools like oscilloscopes and VNAs for hardware validation and debugging
- Identify technical issues and perform root cause analysis for effective resolution
Benefits
- general: Remote work options
- general: Adaptable schedules for work-life balance
- general: Inclusive culture focused on growth, innovation, and excellence
- general: Continuous learning opportunities
- general: Certifications in emerging technologies like cloud and AI
Tags & Categories
Signal Integrity and Power Integrity Engineer
Capgemini
Signal Integrity and Power Integrity Engineer
Job Description
Signal Integrity and Power Integrity Engineer
📋 Job Overview
As a Signal Integrity and Power Integrity Engineer at Capgemini, you will perform high-speed SI/PI simulations and testing for advanced interfaces and platforms. You will collaborate with design and layout teams to optimize signal performance and reliability in complex hardware systems. The role involves analysis, validation, and root cause resolution to ensure robust system design.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Perform pre- and post-layout SI/PI analysis for die, package, and board-level designs
- Conduct simulations using IBIS/IBIS-AMI models and analyze eye diagrams to recommend equalization settings
- Analyze S-parameters including insertion loss, return loss, crosstalk, and TDR
- Provide layout constraints and recommendations to ensure signal integrity
- Select appropriate stack-up materials including dielectric, copper thickness, and impedance control
- Work with high-speed interfaces such as PCIe Gen3/4/5, DDR4/5, LPDDR4/5, 10G Ethernet, and USB 3.2 Gen1/2
- Utilize tools like oscilloscopes and VNAs for hardware validation and debugging
- Identify technical issues and perform root cause analysis for effective resolution
✅ Required Qualifications
- Bachelor’s or Master’s degree in Engineering (BE/B.Tech/M.E/M.Tech or equivalent)
- 7–10 years of experience in high-speed SI/PI simulations and testing
- Strong expertise in interfaces such as PCIe, DDR, LPDDR, Ethernet, and USB
- Hands-on experience with IBIS/IBIS-AMI models and eye diagram analysis
- Proficient in S-parameter analysis and signal integrity metrics
- Knowledge of stack-up design including dielectric selection and impedance control
- Experience providing layout constraints and collaborating with design teams
⭐ Preferred Qualifications
- Experience with oscilloscopes, VNAs, and hardware debugging tools
🛠️ Required Skills
- Signal Integrity (SI) simulations
- Power Integrity (PI) simulations
- IBIS/IBIS-AMI models
- Eye diagram analysis
- Equalization settings
- S-parameter analysis
- Insertion loss
- Return loss
- Crosstalk
- TDR (Time Domain Reflectometry)
- Layout constraints
- Stack-up design
- Dielectric selection
- Copper thickness
- Impedance control
- High-speed interfaces: PCIe Gen3/4/5, DDR4/5, LPDDR4/5, 10G Ethernet, USB 3.2 Gen1/2
- Oscilloscopes
- VNAs (Vector Network Analyzers)
- Hardware validation and debugging
- Root cause analysis
- Collaboration with design and layout teams
🎁 Benefits & Perks
- Remote work options
- Adaptable schedules for work-life balance
- Inclusive culture focused on growth, innovation, and excellence
- Continuous learning opportunities
- Certifications in emerging technologies like cloud and AI
Locations
- Bangalore, India
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Signal Integrity (SI) simulationsintermediate
- Power Integrity (PI) simulationsintermediate
- IBIS/IBIS-AMI modelsintermediate
- Eye diagram analysisintermediate
- Equalization settingsintermediate
- S-parameter analysisintermediate
- Insertion lossintermediate
- Return lossintermediate
- Crosstalkintermediate
- TDR (Time Domain Reflectometry)intermediate
- Layout constraintsintermediate
- Stack-up designintermediate
- Dielectric selectionintermediate
- Copper thicknessintermediate
- Impedance controlintermediate
- High-speed interfaces: PCIe Gen3/4/5, DDR4/5, LPDDR4/5, 10G Ethernet, USB 3.2 Gen1/2intermediate
- Oscilloscopesintermediate
- VNAs (Vector Network Analyzers)intermediate
- Hardware validation and debuggingintermediate
- Root cause analysisintermediate
- Collaboration with design and layout teamsintermediate
Required Qualifications
- Bachelor’s or Master’s degree in Engineering (BE/B.Tech/M.E/M.Tech or equivalent) (experience)
- 7–10 years of experience in high-speed SI/PI simulations and testing (experience)
- Strong expertise in interfaces such as PCIe, DDR, LPDDR, Ethernet, and USB (experience)
- Hands-on experience with IBIS/IBIS-AMI models and eye diagram analysis (experience)
- Proficient in S-parameter analysis and signal integrity metrics (experience)
- Knowledge of stack-up design including dielectric selection and impedance control (experience)
- Experience providing layout constraints and collaborating with design teams (experience)
Preferred Qualifications
- Experience with oscilloscopes, VNAs, and hardware debugging tools (experience)
Responsibilities
- Perform pre- and post-layout SI/PI analysis for die, package, and board-level designs
- Conduct simulations using IBIS/IBIS-AMI models and analyze eye diagrams to recommend equalization settings
- Analyze S-parameters including insertion loss, return loss, crosstalk, and TDR
- Provide layout constraints and recommendations to ensure signal integrity
- Select appropriate stack-up materials including dielectric, copper thickness, and impedance control
- Work with high-speed interfaces such as PCIe Gen3/4/5, DDR4/5, LPDDR4/5, 10G Ethernet, and USB 3.2 Gen1/2
- Utilize tools like oscilloscopes and VNAs for hardware validation and debugging
- Identify technical issues and perform root cause analysis for effective resolution
Benefits
- general: Remote work options
- general: Adaptable schedules for work-life balance
- general: Inclusive culture focused on growth, innovation, and excellence
- general: Continuous learning opportunities
- general: Certifications in emerging technologies like cloud and AI
Tags & Categories