STA Engineer
Capgemini
STA Engineer
Job Description
STA Engineer
📋 Job Overview
As an STA Engineer at Capgemini, you will handle timing closure and verification for complex ASIC and SoC designs, collaborating with cross-functional teams to meet timing requirements across design stages. The role involves owning full-chip and block-level timing analysis, developing SDC constraints, and optimizing paths using industry-standard tools. You will also automate STA flows and support test mode closures in advanced process nodes.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages
- Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs
- Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus)
- Collaborate with design and architecture teams to define timing requirements and resolve violations
- Analyze timing scenarios, margins, and corner cases
- Integrate third-party IPs and derive timing signoff requirements
- Optimize timing paths and reduce signoff corners by merging modes
- Automate STA flows using scripting languages
- Support test mode timing closure (e.g., scan shift, scan capture, BIST)
✅ Required Qualifications
- Strong expertise in Static Timing Analysis (STA) using tools like Synopsys PrimeTime and Cadence Tempus
- Proficient in writing and validating SDC constraints
- Skilled in TCL, Perl, Python for automation
- Solid understanding of ASIC/SoC design flows, including synthesis and physical design
- Experience with corner and mode analysis, process variations, and signal integrity
- Experience integrating custom IPs (PLLs, SerDes, ADC/DAC, GPIO, HSIO)
⭐ Preferred Qualifications
- Familiarity with constraint debugging tools like Synopsys GCA (Galaxy Constraint Analyzer)
- Exposure to tools such as Genus, Timevision, Fishtail, Tweaker
- Knowledge of low-power design techniques (UPF, multi-voltage domains, power gating)
- Familiarity with advanced process nodes (3nm, 5nm, 7nm, FinFET)
- Strong communication and collaboration skills
- Ability to mentor junior engineers
🛠️ Required Skills
- Static Timing Analysis (STA)
- Synopsys PrimeTime
- Cadence Tempus
- SDC constraints
- TCL
- Perl
- Python
- ASIC/SoC design flows
- Synthesis
- Physical design
- Corner and mode analysis
- Process variations
- Signal integrity
- Synopsys GCA (Galaxy Constraint Analyzer)
- Genus
- Timevision
- Fishtail
- Tweaker
- Low-power design techniques
- UPF
- Multi-voltage domains
- Power gating
- Custom IPs (PLLs, SerDes, ADC/DAC, GPIO, HSIO)
- Communication skills
- Collaboration skills
- Mentoring
- Advanced process nodes (3nm, 5nm, 7nm, FinFET)
🎁 Benefits & Perks
- Collaborative environment
- Continuous learning opportunities
- Chance to work on industry-leading SoC designs
- Culture valuing innovation, technical excellence, and work-life balance
Locations
- Bangalore, India
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Static Timing Analysis (STA)intermediate
- Synopsys PrimeTimeintermediate
- Cadence Tempusintermediate
- SDC constraintsintermediate
- TCLintermediate
- Perlintermediate
- Pythonintermediate
- ASIC/SoC design flowsintermediate
- Synthesisintermediate
- Physical designintermediate
- Corner and mode analysisintermediate
- Process variationsintermediate
- Signal integrityintermediate
- Synopsys GCA (Galaxy Constraint Analyzer)intermediate
- Genusintermediate
- Timevisionintermediate
- Fishtailintermediate
- Tweakerintermediate
- Low-power design techniquesintermediate
- UPFintermediate
- Multi-voltage domainsintermediate
- Power gatingintermediate
- Custom IPs (PLLs, SerDes, ADC/DAC, GPIO, HSIO)intermediate
- Communication skillsintermediate
- Collaboration skillsintermediate
- Mentoringintermediate
- Advanced process nodes (3nm, 5nm, 7nm, FinFET)intermediate
Required Qualifications
- Strong expertise in Static Timing Analysis (STA) using tools like Synopsys PrimeTime and Cadence Tempus (experience)
- Proficient in writing and validating SDC constraints (experience)
- Skilled in TCL, Perl, Python for automation (experience)
- Solid understanding of ASIC/SoC design flows, including synthesis and physical design (experience)
- Experience with corner and mode analysis, process variations, and signal integrity (experience)
- Experience integrating custom IPs (PLLs, SerDes, ADC/DAC, GPIO, HSIO) (experience)
Preferred Qualifications
- Familiarity with constraint debugging tools like Synopsys GCA (Galaxy Constraint Analyzer) (experience)
- Exposure to tools such as Genus, Timevision, Fishtail, Tweaker (experience)
- Knowledge of low-power design techniques (UPF, multi-voltage domains, power gating) (experience)
- Familiarity with advanced process nodes (3nm, 5nm, 7nm, FinFET) (experience)
- Strong communication and collaboration skills (experience)
- Ability to mentor junior engineers (experience)
Responsibilities
- Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages
- Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs
- Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus)
- Collaborate with design and architecture teams to define timing requirements and resolve violations
- Analyze timing scenarios, margins, and corner cases
- Integrate third-party IPs and derive timing signoff requirements
- Optimize timing paths and reduce signoff corners by merging modes
- Automate STA flows using scripting languages
- Support test mode timing closure (e.g., scan shift, scan capture, BIST)
Benefits
- general: Collaborative environment
- general: Continuous learning opportunities
- general: Chance to work on industry-leading SoC designs
- general: Culture valuing innovation, technical excellence, and work-life balance
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STA Engineer
Capgemini
STA Engineer
Job Description
STA Engineer
📋 Job Overview
As an STA Engineer at Capgemini, you will handle timing closure and verification for complex ASIC and SoC designs, collaborating with cross-functional teams to meet timing requirements across design stages. The role involves owning full-chip and block-level timing analysis, developing SDC constraints, and optimizing paths using industry-standard tools. You will also automate STA flows and support test mode closures in advanced process nodes.
📍 Location: Bangalore
💼 Experience Level: Experienced Professionals
🏢 Business Unit: Engineering and RandD Services
🎯 Key Responsibilities
- Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages
- Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs
- Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus)
- Collaborate with design and architecture teams to define timing requirements and resolve violations
- Analyze timing scenarios, margins, and corner cases
- Integrate third-party IPs and derive timing signoff requirements
- Optimize timing paths and reduce signoff corners by merging modes
- Automate STA flows using scripting languages
- Support test mode timing closure (e.g., scan shift, scan capture, BIST)
✅ Required Qualifications
- Strong expertise in Static Timing Analysis (STA) using tools like Synopsys PrimeTime and Cadence Tempus
- Proficient in writing and validating SDC constraints
- Skilled in TCL, Perl, Python for automation
- Solid understanding of ASIC/SoC design flows, including synthesis and physical design
- Experience with corner and mode analysis, process variations, and signal integrity
- Experience integrating custom IPs (PLLs, SerDes, ADC/DAC, GPIO, HSIO)
⭐ Preferred Qualifications
- Familiarity with constraint debugging tools like Synopsys GCA (Galaxy Constraint Analyzer)
- Exposure to tools such as Genus, Timevision, Fishtail, Tweaker
- Knowledge of low-power design techniques (UPF, multi-voltage domains, power gating)
- Familiarity with advanced process nodes (3nm, 5nm, 7nm, FinFET)
- Strong communication and collaboration skills
- Ability to mentor junior engineers
🛠️ Required Skills
- Static Timing Analysis (STA)
- Synopsys PrimeTime
- Cadence Tempus
- SDC constraints
- TCL
- Perl
- Python
- ASIC/SoC design flows
- Synthesis
- Physical design
- Corner and mode analysis
- Process variations
- Signal integrity
- Synopsys GCA (Galaxy Constraint Analyzer)
- Genus
- Timevision
- Fishtail
- Tweaker
- Low-power design techniques
- UPF
- Multi-voltage domains
- Power gating
- Custom IPs (PLLs, SerDes, ADC/DAC, GPIO, HSIO)
- Communication skills
- Collaboration skills
- Mentoring
- Advanced process nodes (3nm, 5nm, 7nm, FinFET)
🎁 Benefits & Perks
- Collaborative environment
- Continuous learning opportunities
- Chance to work on industry-leading SoC designs
- Culture valuing innovation, technical excellence, and work-life balance
Locations
- Bangalore, India
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Static Timing Analysis (STA)intermediate
- Synopsys PrimeTimeintermediate
- Cadence Tempusintermediate
- SDC constraintsintermediate
- TCLintermediate
- Perlintermediate
- Pythonintermediate
- ASIC/SoC design flowsintermediate
- Synthesisintermediate
- Physical designintermediate
- Corner and mode analysisintermediate
- Process variationsintermediate
- Signal integrityintermediate
- Synopsys GCA (Galaxy Constraint Analyzer)intermediate
- Genusintermediate
- Timevisionintermediate
- Fishtailintermediate
- Tweakerintermediate
- Low-power design techniquesintermediate
- UPFintermediate
- Multi-voltage domainsintermediate
- Power gatingintermediate
- Custom IPs (PLLs, SerDes, ADC/DAC, GPIO, HSIO)intermediate
- Communication skillsintermediate
- Collaboration skillsintermediate
- Mentoringintermediate
- Advanced process nodes (3nm, 5nm, 7nm, FinFET)intermediate
Required Qualifications
- Strong expertise in Static Timing Analysis (STA) using tools like Synopsys PrimeTime and Cadence Tempus (experience)
- Proficient in writing and validating SDC constraints (experience)
- Skilled in TCL, Perl, Python for automation (experience)
- Solid understanding of ASIC/SoC design flows, including synthesis and physical design (experience)
- Experience with corner and mode analysis, process variations, and signal integrity (experience)
- Experience integrating custom IPs (PLLs, SerDes, ADC/DAC, GPIO, HSIO) (experience)
Preferred Qualifications
- Familiarity with constraint debugging tools like Synopsys GCA (Galaxy Constraint Analyzer) (experience)
- Exposure to tools such as Genus, Timevision, Fishtail, Tweaker (experience)
- Knowledge of low-power design techniques (UPF, multi-voltage domains, power gating) (experience)
- Familiarity with advanced process nodes (3nm, 5nm, 7nm, FinFET) (experience)
- Strong communication and collaboration skills (experience)
- Ability to mentor junior engineers (experience)
Responsibilities
- Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages
- Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs
- Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus)
- Collaborate with design and architecture teams to define timing requirements and resolve violations
- Analyze timing scenarios, margins, and corner cases
- Integrate third-party IPs and derive timing signoff requirements
- Optimize timing paths and reduce signoff corners by merging modes
- Automate STA flows using scripting languages
- Support test mode timing closure (e.g., scan shift, scan capture, BIST)
Benefits
- general: Collaborative environment
- general: Continuous learning opportunities
- general: Chance to work on industry-leading SoC designs
- general: Culture valuing innovation, technical excellence, and work-life balance
Tags & Categories
Answer 10 quick questions to check your fit for STA Engineer @ Capgemini.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs