Static Timing Analysis Engineer
Capgemini
Static Timing Analysis Engineer
Job Description
Static Timing Analysis Engineer
š Job Overview
The Static Timing Analysis Engineer at Capgemini Engineering performs comprehensive timing analysis and closure for full-chip, sub-system, and IP levels in VLSI designs. The role involves developing and validating timing constraints, integrating STA tools into design flows, and providing expert guidance on methodologies to achieve performance goals. This position requires deep technical knowledge in STA concepts and collaboration with cross-functional teams to ensure seamless timing closure.
š Location: Coimbatore
š¼ Experience Level: Experienced Professionals
š¢ Business Unit: Engineering and RandD Services
šÆ Key Responsibilities
- Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels
- Achieve timing closure by resolving violations and optimizing paths
- Define and validate timing constraints (clocks, I/O delays, false/multi-cycle paths)
- Integrate constraints from multiple IPs for hierarchical STA
- Use STA tools like Synopsys PrimeTime, Cadence Tempus, or equivalent
- Integrate STA into the overall design flow and automate processes for efficiency
- Provide expert guidance on STA methodologies, including setup and hold time analysis, clock domain crossing, and multi-cycle paths
- Define and implement timing constraints from scratch such as clock definitions, input/output delays, and path constraints
- Integrate existing timing constraints from various IP for Full-Chip/Sub-system timing analysis
- Guide the integration of STA tools into the overall design flow, ensuring compatibility and optimal performance
- Oversee the process of achieving timing closure, addressing timing violations and guiding optimizations
ā Required Qualifications
- Bachelorās or Masterās Degree in Electrical Engineering, Electronics & Communication Engineering, VLSI Design, Computer Engineering or related fields
- In-depth understanding of STA concepts, EDA tools, and methodologies
- Experience in timing constraints development and timing closure for Full-Chip/Sub-system to meet design performance
ā Preferred Qualifications
- Experience in leading teams and mentoring less experienced engineers in STA practice
š ļø Required Skills
- STA concepts
- EDA tools
- Methodologies
- Timing constraints development
- Timing closure
- Setup and hold time analysis
- Clock domain crossing
- Multi-cycle paths
- Synopsys PrimeTime
- Cadence Tempus
- Mentor Graphics' ModelSim
- Problem-solving abilities
- Analytical skills
- Communication skills
- Leadership
- Mentoring
- Design flow management
- Flow automation
- Cross-functional coordination
- RTL design collaboration
- Physical design collaboration
- Verification collaboration
- Manufacturing collaboration
Locations
- Coimbatore, India
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- STA conceptsintermediate
- EDA toolsintermediate
- Methodologiesintermediate
- Timing constraints developmentintermediate
- Timing closureintermediate
- Setup and hold time analysisintermediate
- Clock domain crossingintermediate
- Multi-cycle pathsintermediate
- Synopsys PrimeTimeintermediate
- Cadence Tempusintermediate
- Mentor Graphics' ModelSimintermediate
- Problem-solving abilitiesintermediate
- Analytical skillsintermediate
- Communication skillsintermediate
- Leadershipintermediate
- Mentoringintermediate
- Design flow managementintermediate
- Flow automationintermediate
- Cross-functional coordinationintermediate
- RTL design collaborationintermediate
- Physical design collaborationintermediate
- Verification collaborationintermediate
- Manufacturing collaborationintermediate
Required Qualifications
- Bachelorās or Masterās Degree in Electrical Engineering, Electronics & Communication Engineering, VLSI Design, Computer Engineering or related fields (experience)
- In-depth understanding of STA concepts, EDA tools, and methodologies (experience)
- Experience in timing constraints development and timing closure for Full-Chip/Sub-system to meet design performance (experience)
Preferred Qualifications
- Experience in leading teams and mentoring less experienced engineers in STA practice (experience)
Responsibilities
- Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels
- Achieve timing closure by resolving violations and optimizing paths
- Define and validate timing constraints (clocks, I/O delays, false/multi-cycle paths)
- Integrate constraints from multiple IPs for hierarchical STA
- Use STA tools like Synopsys PrimeTime, Cadence Tempus, or equivalent
- Integrate STA into the overall design flow and automate processes for efficiency
- Provide expert guidance on STA methodologies, including setup and hold time analysis, clock domain crossing, and multi-cycle paths
- Define and implement timing constraints from scratch such as clock definitions, input/output delays, and path constraints
- Integrate existing timing constraints from various IP for Full-Chip/Sub-system timing analysis
- Guide the integration of STA tools into the overall design flow, ensuring compatibility and optimal performance
- Oversee the process of achieving timing closure, addressing timing violations and guiding optimizations
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Static Timing Analysis Engineer
Capgemini
Static Timing Analysis Engineer
Job Description
Static Timing Analysis Engineer
š Job Overview
The Static Timing Analysis Engineer at Capgemini Engineering performs comprehensive timing analysis and closure for full-chip, sub-system, and IP levels in VLSI designs. The role involves developing and validating timing constraints, integrating STA tools into design flows, and providing expert guidance on methodologies to achieve performance goals. This position requires deep technical knowledge in STA concepts and collaboration with cross-functional teams to ensure seamless timing closure.
š Location: Coimbatore
š¼ Experience Level: Experienced Professionals
š¢ Business Unit: Engineering and RandD Services
šÆ Key Responsibilities
- Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels
- Achieve timing closure by resolving violations and optimizing paths
- Define and validate timing constraints (clocks, I/O delays, false/multi-cycle paths)
- Integrate constraints from multiple IPs for hierarchical STA
- Use STA tools like Synopsys PrimeTime, Cadence Tempus, or equivalent
- Integrate STA into the overall design flow and automate processes for efficiency
- Provide expert guidance on STA methodologies, including setup and hold time analysis, clock domain crossing, and multi-cycle paths
- Define and implement timing constraints from scratch such as clock definitions, input/output delays, and path constraints
- Integrate existing timing constraints from various IP for Full-Chip/Sub-system timing analysis
- Guide the integration of STA tools into the overall design flow, ensuring compatibility and optimal performance
- Oversee the process of achieving timing closure, addressing timing violations and guiding optimizations
ā Required Qualifications
- Bachelorās or Masterās Degree in Electrical Engineering, Electronics & Communication Engineering, VLSI Design, Computer Engineering or related fields
- In-depth understanding of STA concepts, EDA tools, and methodologies
- Experience in timing constraints development and timing closure for Full-Chip/Sub-system to meet design performance
ā Preferred Qualifications
- Experience in leading teams and mentoring less experienced engineers in STA practice
š ļø Required Skills
- STA concepts
- EDA tools
- Methodologies
- Timing constraints development
- Timing closure
- Setup and hold time analysis
- Clock domain crossing
- Multi-cycle paths
- Synopsys PrimeTime
- Cadence Tempus
- Mentor Graphics' ModelSim
- Problem-solving abilities
- Analytical skills
- Communication skills
- Leadership
- Mentoring
- Design flow management
- Flow automation
- Cross-functional coordination
- RTL design collaboration
- Physical design collaboration
- Verification collaboration
- Manufacturing collaboration
Locations
- Coimbatore, India
Salary
Estimated Salary Rangemedium confidence
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- STA conceptsintermediate
- EDA toolsintermediate
- Methodologiesintermediate
- Timing constraints developmentintermediate
- Timing closureintermediate
- Setup and hold time analysisintermediate
- Clock domain crossingintermediate
- Multi-cycle pathsintermediate
- Synopsys PrimeTimeintermediate
- Cadence Tempusintermediate
- Mentor Graphics' ModelSimintermediate
- Problem-solving abilitiesintermediate
- Analytical skillsintermediate
- Communication skillsintermediate
- Leadershipintermediate
- Mentoringintermediate
- Design flow managementintermediate
- Flow automationintermediate
- Cross-functional coordinationintermediate
- RTL design collaborationintermediate
- Physical design collaborationintermediate
- Verification collaborationintermediate
- Manufacturing collaborationintermediate
Required Qualifications
- Bachelorās or Masterās Degree in Electrical Engineering, Electronics & Communication Engineering, VLSI Design, Computer Engineering or related fields (experience)
- In-depth understanding of STA concepts, EDA tools, and methodologies (experience)
- Experience in timing constraints development and timing closure for Full-Chip/Sub-system to meet design performance (experience)
Preferred Qualifications
- Experience in leading teams and mentoring less experienced engineers in STA practice (experience)
Responsibilities
- Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels
- Achieve timing closure by resolving violations and optimizing paths
- Define and validate timing constraints (clocks, I/O delays, false/multi-cycle paths)
- Integrate constraints from multiple IPs for hierarchical STA
- Use STA tools like Synopsys PrimeTime, Cadence Tempus, or equivalent
- Integrate STA into the overall design flow and automate processes for efficiency
- Provide expert guidance on STA methodologies, including setup and hold time analysis, clock domain crossing, and multi-cycle paths
- Define and implement timing constraints from scratch such as clock definitions, input/output delays, and path constraints
- Integrate existing timing constraints from various IP for Full-Chip/Sub-system timing analysis
- Guide the integration of STA tools into the overall design flow, ensuring compatibility and optimal performance
- Oversee the process of achieving timing closure, addressing timing violations and guiding optimizations
Tags & Categories
Answer 10 quick questions to check your fit for Static Timing Analysis Engineer @ Capgemini.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs