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ASIC Logic Design Engineering Technical Leader

Cisco

ASIC Logic Design Engineering Technical Leader

full-timePosted: Dec 24, 2025

Job Description

Job ID: 2001803

Meet the Team
Join the Cisco Silicon One Front-End Design team, at the core of Cisco’s silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of what’s possible.
Cisco Silicon One™ is transforming the industry with a unified, programmable architecture powering Cisco’s future routing portfolio and shaping the Internet for decades to come.

Your Impact

  • Write and review micro-architecture specifications
  • Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
  • Contribute to full chip integration, timing methodology, and analysis
  • Collaborate with verification engineers to resolve bugs and achieve coverage closure
  • Work with the physical design team to close timing and PnR issues
  • Support design methodology evolution and best practices
  • Perform debug, root-cause analysis, and post-silicon validation in the lab


Minimum Qualifications

  • B.Sc./M.Sc. in Electrical Engineering from a top university
  • ​Minimum of 8 years of proven experience in a relevant field
  • RTL design experience
  • Familiarity with UVM and functional verification methodologies


Preferred Qualifications

  • Experience with MATLAB simulations and bit-exact modeling environments
  • Familiarity with mixed-signal systems and environments
  • Knowledge and hands-on experience with Clock Domain Crossing (CDC)

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

Locations

  • Caesarea, Israel
  • Tel Aviv-Yafo, Israel

Salary

453,200 - 597,000 USD / yearly

Skills Required

  • RTL design (Verilog/SystemVerilog)intermediate
  • Micro-architecture specificationsintermediate
  • Timing, performance, and power analysisintermediate
  • Full chip integrationintermediate
  • UVM and functional verification methodologiesintermediate
  • Clock Domain Crossing (CDC)intermediate

Required Qualifications

  • B.Sc./M.Sc. in Electrical Engineering from a top university (experience)
  • Minimum of 8 years of proven experience in a relevant field (experience)
  • RTL design experience (experience)
  • Familiarity with UVM and functional verification methodologies (experience)

Preferred Qualifications

  • Experience with MATLAB simulations and bit-exact modeling environments (experience)
  • Familiarity with mixed-signal systems and environments (experience)
  • Knowledge and hands-on experience with Clock Domain Crossing (CDC) (experience)

Responsibilities

  • Write and review micro-architecture specifications
  • Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
  • Contribute to full chip integration, timing methodology, and analysis
  • Collaborate with verification engineers to resolve bugs and achieve coverage closure
  • Work with the physical design team to close timing and PnR issues
  • Support design methodology evolution and best practices
  • Perform debug, root-cause analysis, and post-silicon validation in the lab

Benefits

  • general: Worldwide network of doers and experts
  • general: Opportunities to grow and build are limitless
  • general: Work as a team, collaborating with empathy to make really big things happen on a global scale

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Cisco logo

ASIC Logic Design Engineering Technical Leader

Cisco

ASIC Logic Design Engineering Technical Leader

full-timePosted: Dec 24, 2025

Job Description

Job ID: 2001803

Meet the Team
Join the Cisco Silicon One Front-End Design team, at the core of Cisco’s silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of what’s possible.
Cisco Silicon One™ is transforming the industry with a unified, programmable architecture powering Cisco’s future routing portfolio and shaping the Internet for decades to come.

Your Impact

  • Write and review micro-architecture specifications
  • Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
  • Contribute to full chip integration, timing methodology, and analysis
  • Collaborate with verification engineers to resolve bugs and achieve coverage closure
  • Work with the physical design team to close timing and PnR issues
  • Support design methodology evolution and best practices
  • Perform debug, root-cause analysis, and post-silicon validation in the lab


Minimum Qualifications

  • B.Sc./M.Sc. in Electrical Engineering from a top university
  • ​Minimum of 8 years of proven experience in a relevant field
  • RTL design experience
  • Familiarity with UVM and functional verification methodologies


Preferred Qualifications

  • Experience with MATLAB simulations and bit-exact modeling environments
  • Familiarity with mixed-signal systems and environments
  • Knowledge and hands-on experience with Clock Domain Crossing (CDC)

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

Locations

  • Caesarea, Israel
  • Tel Aviv-Yafo, Israel

Salary

453,200 - 597,000 USD / yearly

Skills Required

  • RTL design (Verilog/SystemVerilog)intermediate
  • Micro-architecture specificationsintermediate
  • Timing, performance, and power analysisintermediate
  • Full chip integrationintermediate
  • UVM and functional verification methodologiesintermediate
  • Clock Domain Crossing (CDC)intermediate

Required Qualifications

  • B.Sc./M.Sc. in Electrical Engineering from a top university (experience)
  • Minimum of 8 years of proven experience in a relevant field (experience)
  • RTL design experience (experience)
  • Familiarity with UVM and functional verification methodologies (experience)

Preferred Qualifications

  • Experience with MATLAB simulations and bit-exact modeling environments (experience)
  • Familiarity with mixed-signal systems and environments (experience)
  • Knowledge and hands-on experience with Clock Domain Crossing (CDC) (experience)

Responsibilities

  • Write and review micro-architecture specifications
  • Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
  • Contribute to full chip integration, timing methodology, and analysis
  • Collaborate with verification engineers to resolve bugs and achieve coverage closure
  • Work with the physical design team to close timing and PnR issues
  • Support design methodology evolution and best practices
  • Perform debug, root-cause analysis, and post-silicon validation in the lab

Benefits

  • general: Worldwide network of doers and experts
  • general: Opportunities to grow and build are limitless
  • general: Work as a team, collaborating with empathy to make really big things happen on a global scale

Target Your Resume for "ASIC Logic Design Engineering Technical Leader" , Cisco

Get personalized recommendations to optimize your resume specifically for ASIC Logic Design Engineering Technical Leader. Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "ASIC Logic Design Engineering Technical Leader" , Cisco

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score
Quiz Challenge

Answer 10 quick questions to check your fit for ASIC Logic Design Engineering Technical Leader @ Cisco.

10 Questions
~2 Minutes
Instant Score

Related Books and Jobs

No related jobs found at the moment.