Hardware Engineer- FPGA, RTL Design, Verilog
Cisco
Hardware Engineer- FPGA, RTL Design, Verilog
Job Description
Job ID: 2005237
Meet the Team
We are part of the Common Hardware Group, with our team specializing in FPGA development. Our work spans both sophisticated data-path and challenging control-path FPGAs. The design process includes crafting the FPGA functional specification document, RTL coding, image generation and validation. We leverage industry-standard tools for FPGA design, incorporating various quality metrics to ensure a robust process. Our ultimate goal is to deliver bug-free RTL for first-pass success on the board. Additionally, we collaborate closely with our remote teams based in US and Italy.
Your Impact
* Design and implementation of FPGAs.
* Participate in the architecture definition, implementation and verification phases.
* Detailed design specification and test plan development.
* Develop and implement block level RTL, perform synthesis and achieve timing closure.
* Work with multi-functional teams (hardware, software, diagnostics and signal integrity groups).
* Assist in complex subsystem level lab bring-up, integration, and unit test validation.
* Contribution to the design process adoption with in the team.
Minimum Qualifications
*Educational Background: Requires 5+ years of experience in FPGA designs with MTech/BTech in EE/EC domain.
* Experienced in crafting with Xilinx, Altera and Microsemi FPGAs or Proficiency in HDL languages (Verilog, VHDL and System Verilog)
* Hands on experience with FPGA vendor tools like Vivado, Quartus and Libero
* Hands-on experience with Ethernet based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART etc. Familiarity with simulation flow like UVM and VMM will be an added advantage
* Basic knowledge on Unix system and script tool.
Preferred Qualifications
* Knowledge on the signal integrity and system bring-up.
* Good English written and verbal communications. Self-motivation, partnership and strong interpersonal skills are needed.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Locations
- Bangalore, India
Salary
2,512,800 - 3,604,100 INR / yearly
Skills Required
- FPGA designsintermediate
- HDL languages (Verilog, VHDL, System Verilog)intermediate
- FPGA vendor tools (Vivado, Quartus, Libero)intermediate
- Ethernet based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UARTintermediate
- Simulation flow (UVM, VMM)intermediate
- Unix system and scriptingintermediate
- Xilinx, Altera, Microsemi FPGAsintermediate
- RTL coding, synthesis, timing closureintermediate
Required Qualifications
- Educational Background: Requires 5+ years of experience in FPGA designs with MTech/BTech in EE/EC domain. (experience)
- Experienced in crafting with Xilinx, Altera and Microsemi FPGAs or Proficiency in HDL languages (Verilog, VHDL and System Verilog) (experience)
- Hands on experience with FPGA vendor tools like Vivado, Quartus and Libero (experience)
- Hands-on experience with Ethernet based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART etc. Familiarity with simulation flow like UVM and VMM will be an added advantage (experience)
- Basic knowledge on Unix system and script tool. (experience)
Preferred Qualifications
- Knowledge on the signal integrity and system bring-up. (experience)
- Good English written and verbal communications. Self-motivation, partnership and strong interpersonal skills are needed. (experience)
Responsibilities
- Design and implementation of FPGAs.
- Participate in the architecture definition, implementation and verification phases.
- Detailed design specification and test plan development.
- Develop and implement block level RTL, perform synthesis and achieve timing closure.
- Work with multi-functional teams (hardware, software, diagnostics and signal integrity groups).
- Assist in complex subsystem level lab bring-up, integration, and unit test validation.
- Contribution to the design process adoption with in the team.
Benefits
- general: Global opportunities to grow and build
- general: Collaborative team environment
- general: Work on innovative solutions with worldwide impact
Answer 10 quick questions to check your fit for Hardware Engineer- FPGA, RTL Design, Verilog @ Cisco.
Hardware Engineer- FPGA, RTL Design, Verilog
Cisco
Hardware Engineer- FPGA, RTL Design, Verilog
Job Description
Job ID: 2005237
Meet the Team
We are part of the Common Hardware Group, with our team specializing in FPGA development. Our work spans both sophisticated data-path and challenging control-path FPGAs. The design process includes crafting the FPGA functional specification document, RTL coding, image generation and validation. We leverage industry-standard tools for FPGA design, incorporating various quality metrics to ensure a robust process. Our ultimate goal is to deliver bug-free RTL for first-pass success on the board. Additionally, we collaborate closely with our remote teams based in US and Italy.
Your Impact
* Design and implementation of FPGAs.
* Participate in the architecture definition, implementation and verification phases.
* Detailed design specification and test plan development.
* Develop and implement block level RTL, perform synthesis and achieve timing closure.
* Work with multi-functional teams (hardware, software, diagnostics and signal integrity groups).
* Assist in complex subsystem level lab bring-up, integration, and unit test validation.
* Contribution to the design process adoption with in the team.
Minimum Qualifications
*Educational Background: Requires 5+ years of experience in FPGA designs with MTech/BTech in EE/EC domain.
* Experienced in crafting with Xilinx, Altera and Microsemi FPGAs or Proficiency in HDL languages (Verilog, VHDL and System Verilog)
* Hands on experience with FPGA vendor tools like Vivado, Quartus and Libero
* Hands-on experience with Ethernet based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART etc. Familiarity with simulation flow like UVM and VMM will be an added advantage
* Basic knowledge on Unix system and script tool.
Preferred Qualifications
* Knowledge on the signal integrity and system bring-up.
* Good English written and verbal communications. Self-motivation, partnership and strong interpersonal skills are needed.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Locations
- Bangalore, India
Salary
2,512,800 - 3,604,100 INR / yearly
Skills Required
- FPGA designsintermediate
- HDL languages (Verilog, VHDL, System Verilog)intermediate
- FPGA vendor tools (Vivado, Quartus, Libero)intermediate
- Ethernet based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UARTintermediate
- Simulation flow (UVM, VMM)intermediate
- Unix system and scriptingintermediate
- Xilinx, Altera, Microsemi FPGAsintermediate
- RTL coding, synthesis, timing closureintermediate
Required Qualifications
- Educational Background: Requires 5+ years of experience in FPGA designs with MTech/BTech in EE/EC domain. (experience)
- Experienced in crafting with Xilinx, Altera and Microsemi FPGAs or Proficiency in HDL languages (Verilog, VHDL and System Verilog) (experience)
- Hands on experience with FPGA vendor tools like Vivado, Quartus and Libero (experience)
- Hands-on experience with Ethernet based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART etc. Familiarity with simulation flow like UVM and VMM will be an added advantage (experience)
- Basic knowledge on Unix system and script tool. (experience)
Preferred Qualifications
- Knowledge on the signal integrity and system bring-up. (experience)
- Good English written and verbal communications. Self-motivation, partnership and strong interpersonal skills are needed. (experience)
Responsibilities
- Design and implementation of FPGAs.
- Participate in the architecture definition, implementation and verification phases.
- Detailed design specification and test plan development.
- Develop and implement block level RTL, perform synthesis and achieve timing closure.
- Work with multi-functional teams (hardware, software, diagnostics and signal integrity groups).
- Assist in complex subsystem level lab bring-up, integration, and unit test validation.
- Contribution to the design process adoption with in the team.
Benefits
- general: Global opportunities to grow and build
- general: Collaborative team environment
- general: Work on innovative solutions with worldwide impact
Answer 10 quick questions to check your fit for Hardware Engineer- FPGA, RTL Design, Verilog @ Cisco.