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PD Signoff Methodology Engineer

Cisco

Engineering Jobs

PD Signoff Methodology Engineer

full-timePosted: Nov 13, 2025

Job Description

Job ID: 1451960

This is a hybrid role with four days per week at Cisco’s Yerevan office.

Meet the Team

You'll be joining our CAD Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This team is a critical part of the group leading the development of high-quality VLSI designs and supports the creation of advanced silicon. Our design center brings together all silicon hardware and software development fields, encouraging collaboration and technical excellence.

Your Impact

As part of our team, you’ll help develop and improve flows for all signoff disciplines and contribute to the evolution of implementation tool flows. You’ll play a key role in enabling the delivery of high-performance, large-scale, and complex devices that push the boundaries of what’s possible in chip design.

  • Develop and refine backend methodologies and flows from RTL to GDS, supporting high-quality VLSI design.

  • Contribute to the advancement of all signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure.

  • Collaborate with engineering teams to support and enhance implementation tool flows.

  • Work with advanced silicon technologies and processes to deliver complex and reliable devices.

Minimum Requirements

  • 5+ years of experience as a CAD Physical Design Engineer with PnR and STA or as a  Design Engineer with strong backend design experience.

  • B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or a related field.

  • Strong understanding of STA flows.

  • Familiarity with PnR, physical verification (PV), and formal verification (FV).

Preferred Qualifications

  • Experience in Physical Design CAD, especially with industry-standard EDA tools such as Synopsys or Cadence.

  • Ability to work both independently and within a team.

  • Strong self-learning skills and effective communication.

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

Locations

  • Armenia, Armenia

Salary

0.163 - 0.231 USD / yearly

Skills Required

  • PnR (Place and Route)intermediate
  • STA (Static Timing Analysis)intermediate
  • Physical verification (PV)intermediate
  • Formal verification (FV)intermediate
  • Backend design experienceintermediate
  • EDA tools such as Synopsys or Cadenceintermediate

Required Qualifications

  • 5+ years of experience as a CAD Physical Design Engineer with PnR and STA or as a Design Engineer with strong backend design experience. (experience)
  • B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or a related field. (experience)
  • Strong understanding of STA flows. (experience)
  • Familiarity with PnR, physical verification (PV), and formal verification (FV). (experience)

Preferred Qualifications

  • Experience in Physical Design CAD, especially with industry-standard EDA tools such as Synopsys or Cadence. (experience)
  • Ability to work both independently and within a team. (experience)
  • Strong self-learning skills and effective communication. (experience)

Responsibilities

  • Develop and refine backend methodologies and flows from RTL to GDS, supporting high-quality VLSI design.
  • Contribute to the advancement of all signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure.
  • Collaborate with engineering teams to support and enhance implementation tool flows.
  • Work with advanced silicon technologies and processes to deliver complex and reliable devices.

Benefits

  • general: Hybrid role with four days per week at Cisco’s Yerevan office.
  • general: Worldwide network of doers and experts.
  • general: Opportunities to grow and build are limitless.
  • general: Work as a team, collaborating with empathy to make really big things happen on a global scale.

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Cisco logo

PD Signoff Methodology Engineer

Cisco

Engineering Jobs

PD Signoff Methodology Engineer

full-timePosted: Nov 13, 2025

Job Description

Job ID: 1451960

This is a hybrid role with four days per week at Cisco’s Yerevan office.

Meet the Team

You'll be joining our CAD Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This team is a critical part of the group leading the development of high-quality VLSI designs and supports the creation of advanced silicon. Our design center brings together all silicon hardware and software development fields, encouraging collaboration and technical excellence.

Your Impact

As part of our team, you’ll help develop and improve flows for all signoff disciplines and contribute to the evolution of implementation tool flows. You’ll play a key role in enabling the delivery of high-performance, large-scale, and complex devices that push the boundaries of what’s possible in chip design.

  • Develop and refine backend methodologies and flows from RTL to GDS, supporting high-quality VLSI design.

  • Contribute to the advancement of all signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure.

  • Collaborate with engineering teams to support and enhance implementation tool flows.

  • Work with advanced silicon technologies and processes to deliver complex and reliable devices.

Minimum Requirements

  • 5+ years of experience as a CAD Physical Design Engineer with PnR and STA or as a  Design Engineer with strong backend design experience.

  • B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or a related field.

  • Strong understanding of STA flows.

  • Familiarity with PnR, physical verification (PV), and formal verification (FV).

Preferred Qualifications

  • Experience in Physical Design CAD, especially with industry-standard EDA tools such as Synopsys or Cadence.

  • Ability to work both independently and within a team.

  • Strong self-learning skills and effective communication.

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

Locations

  • Armenia, Armenia

Salary

0.163 - 0.231 USD / yearly

Skills Required

  • PnR (Place and Route)intermediate
  • STA (Static Timing Analysis)intermediate
  • Physical verification (PV)intermediate
  • Formal verification (FV)intermediate
  • Backend design experienceintermediate
  • EDA tools such as Synopsys or Cadenceintermediate

Required Qualifications

  • 5+ years of experience as a CAD Physical Design Engineer with PnR and STA or as a Design Engineer with strong backend design experience. (experience)
  • B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or a related field. (experience)
  • Strong understanding of STA flows. (experience)
  • Familiarity with PnR, physical verification (PV), and formal verification (FV). (experience)

Preferred Qualifications

  • Experience in Physical Design CAD, especially with industry-standard EDA tools such as Synopsys or Cadence. (experience)
  • Ability to work both independently and within a team. (experience)
  • Strong self-learning skills and effective communication. (experience)

Responsibilities

  • Develop and refine backend methodologies and flows from RTL to GDS, supporting high-quality VLSI design.
  • Contribute to the advancement of all signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure.
  • Collaborate with engineering teams to support and enhance implementation tool flows.
  • Work with advanced silicon technologies and processes to deliver complex and reliable devices.

Benefits

  • general: Hybrid role with four days per week at Cisco’s Yerevan office.
  • general: Worldwide network of doers and experts.
  • general: Opportunities to grow and build are limitless.
  • general: Work as a team, collaborating with empathy to make really big things happen on a global scale.

Target Your Resume for "PD Signoff Methodology Engineer" , Cisco

Get personalized recommendations to optimize your resume specifically for PD Signoff Methodology Engineer. Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "PD Signoff Methodology Engineer" , Cisco

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Answer 10 quick questions to check your fit for PD Signoff Methodology Engineer @ Cisco.

Quiz Challenge
10 Questions
~2 Minutes
Instant Score

Related Books and Jobs

No related jobs found at the moment.