Physical Design Engineer III, Silicon
Physical Design Engineer III, Silicon
Job Description
Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with programming languages such as Perl, Python, or TCL. Experience in managing block physical implementation and Quality of Results (QoR). Experience with Application-Specific Integrated Circuit (ASIC) Register-Transfer Level to Graphic Data System (RTL to GDS) implementation for high PPA designs. Location: Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
Locations
- Bengaluru, Karnataka, India
Salary
Estimated Salary Rangemedium confidence
45,000,000 - 75,000,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Perlintermediate (programming)
- Pythonintermediate (programming)
- TCLintermediate (programming)
- Block physical implementationintermediate (physical design)
- Quality of Results (QoR)intermediate (physical design)
- ASIC RTL to GDS implementationadvanced (ASIC design)
- Constraintsadvanced (physical design)
- Synthesisadvanced (physical design)
- Clock Tree Synthesis (CTS)advanced (physical design)
- 7/5/3/2nm nodeadvanced (process technology)
- Innovus or Cadence toolsadvanced (EDA tools)
- Electromigration IR Drop (EMIR)advanced (analysis)
- Static Timing Analysis (STA)advanced (analysis)
- Photon Doppler Velocimetry (PDV)advanced (analysis)
- Logic Equivalence Check (LEC)advanced (verification)
- VC Low Power (VCLP) flowsadvanced (low power design)
Required Qualifications
- Bachelor's degree (degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, 4 years)
- programming languages such as Perl, Python, or TCL (experience, 4 years)
- managing block physical implementation and Quality of Results (QoR) (experience, 4 years)
- ASIC Register-Transfer Level to Graphic Data System (RTL to GDS) implementation for high PPA designs (experience, 4 years)
- Master's degree or PhD (degree in Electrical Engineering, Computer Engineering or Computer Science with computer architecture)
Responsibilities
- Use investigative and simulation techniques to ensure Performance, Power, and Area (PPA) is within defined requirements.
- Collaborate with cross-functional teams to debug failures or performance shortfalls from program goals in lab or simulation.
- Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
- Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign-off or implementation domain to enable cross-functional teams to build and deliver blocks that are rectified by construction and ease convergence efforts.
Benefits
- equal opportunity: Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law.
Tags & Categories
Physical Design Engineer III, Silicon
Physical Design Engineer III, Silicon
Job Description
Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with programming languages such as Perl, Python, or TCL. Experience in managing block physical implementation and Quality of Results (QoR). Experience with Application-Specific Integrated Circuit (ASIC) Register-Transfer Level to Graphic Data System (RTL to GDS) implementation for high PPA designs. Location: Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
Locations
- Bengaluru, Karnataka, India
Salary
Estimated Salary Rangemedium confidence
45,000,000 - 75,000,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Perlintermediate (programming)
- Pythonintermediate (programming)
- TCLintermediate (programming)
- Block physical implementationintermediate (physical design)
- Quality of Results (QoR)intermediate (physical design)
- ASIC RTL to GDS implementationadvanced (ASIC design)
- Constraintsadvanced (physical design)
- Synthesisadvanced (physical design)
- Clock Tree Synthesis (CTS)advanced (physical design)
- 7/5/3/2nm nodeadvanced (process technology)
- Innovus or Cadence toolsadvanced (EDA tools)
- Electromigration IR Drop (EMIR)advanced (analysis)
- Static Timing Analysis (STA)advanced (analysis)
- Photon Doppler Velocimetry (PDV)advanced (analysis)
- Logic Equivalence Check (LEC)advanced (verification)
- VC Low Power (VCLP) flowsadvanced (low power design)
Required Qualifications
- Bachelor's degree (degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, 4 years)
- programming languages such as Perl, Python, or TCL (experience, 4 years)
- managing block physical implementation and Quality of Results (QoR) (experience, 4 years)
- ASIC Register-Transfer Level to Graphic Data System (RTL to GDS) implementation for high PPA designs (experience, 4 years)
- Master's degree or PhD (degree in Electrical Engineering, Computer Engineering or Computer Science with computer architecture)
Responsibilities
- Use investigative and simulation techniques to ensure Performance, Power, and Area (PPA) is within defined requirements.
- Collaborate with cross-functional teams to debug failures or performance shortfalls from program goals in lab or simulation.
- Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
- Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign-off or implementation domain to enable cross-functional teams to build and deliver blocks that are rectified by construction and ease convergence efforts.
Benefits
- equal opportunity: Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law.
Tags & Categories