Google | Bengaluru, Karnataka, India. Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 8 years of experience in micro-architecture and design of graphics or Machine Learning (ML) Intellectual Property (IP), managing Low Precision/Mixed Precision Numerics. 5 years of experience architecting networking Application-Specific Integrated Circuits (ASIC) from specification to production. Experience developing Register-Transfer Level (RTL) for ASIC subsystems using SystemVerilog. Experience in micro-architecture, design, verification, logic synthesis and timing closure. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team developing Artificial Intelligence (AI) accelerators in data centers and have responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation and implementation of the next generation of data center accelerators. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.