Silicon Engineer, Design Verification
Silicon Engineer, Design Verification
Job Description
Google | Bengaluru, Karnataka, India. Minimum qualifications: Bachelor's degree in EE, CE, CS, or related. 1 year creating/using verification components in UVM at IP or Subsystem level. Experience developing and maintaining DV testbenches. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
Locations
- Bengaluru, Karnataka, India
Salary
Estimated Salary Rangemedium confidence
15,000,000 - 35,000,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- UVM methodologyintermediate (Verification)
- SystemVerilogintermediate (Programming)
- Design Verification (DV)intermediate (Hardware)
- AMBA protocols (APB/AXI/ACE)intermediate (Protocols)
- Computer Architectureintermediate (Hardware)
- Image Processingadvanced (Domain Knowledge)
- Computer Visionadvanced (Domain Knowledge)
- Machine Learning IPsadvanced (Domain Knowledge)
- SystemVerilog Assertions (SVA)intermediate (Verification)
- Formal Verificationintermediate (Verification)
Required Qualifications
- Bachelor's degree (degree in Electrical Engineering, Computer Engineering, Computer Science, or related field)
- Creating/using verification components and environments in UVM methodology at IP or Subsystem level (experience, 1 years)
- Developing and maintaining design verification (DV) testbenches, test cases, and test environments (experience)
- Master's degree or PhD (degree in Electrical Engineering, Computer Engineering, or Computer Science with emphasis on computer architecture)
Responsibilities
- Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.
- Plan the verification of digital design blocks by understanding design specifications and collaborating with design engineers to identify key verification scenarios.
- Create and improve constrained-random verification environments using SystemVerilog and UVM. Optionally use SystemVerilog Assertions (SVA) and formal tools for formal verification.
- Perform power-aware simulations and formal verification to validate power management features like clock gating, power gating, and DVFS. Develop and implement power-aware test cases, including stress and corner-case scenarios, for power integrity.
- Develop and execute coverage-driven verification plans to ensure comprehensive coverage of ASIC designs. Collaborate with design engineers to resolve coverage issues and improve design quality.
Benefits
- Equal Opportunity: Google is proud to be an equal opportunity and affirmative action employer committed to building a representative workforce and providing equal employment opportunity regardless of protected characteristics.
- Culture: Creating a culture of belonging.
- Accommodations: Accommodations for applicants with needs by completing the Accommodations for Applicants form.
- Global Collaboration: English proficiency required for efficient global collaboration and communication.
Tags & Categories
Silicon Engineer, Design Verification
Silicon Engineer, Design Verification
Job Description
Google | Bengaluru, Karnataka, India. Minimum qualifications: Bachelor's degree in EE, CE, CS, or related. 1 year creating/using verification components in UVM at IP or Subsystem level. Experience developing and maintaining DV testbenches. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
Locations
- Bengaluru, Karnataka, India
Salary
Estimated Salary Rangemedium confidence
15,000,000 - 35,000,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- UVM methodologyintermediate (Verification)
- SystemVerilogintermediate (Programming)
- Design Verification (DV)intermediate (Hardware)
- AMBA protocols (APB/AXI/ACE)intermediate (Protocols)
- Computer Architectureintermediate (Hardware)
- Image Processingadvanced (Domain Knowledge)
- Computer Visionadvanced (Domain Knowledge)
- Machine Learning IPsadvanced (Domain Knowledge)
- SystemVerilog Assertions (SVA)intermediate (Verification)
- Formal Verificationintermediate (Verification)
Required Qualifications
- Bachelor's degree (degree in Electrical Engineering, Computer Engineering, Computer Science, or related field)
- Creating/using verification components and environments in UVM methodology at IP or Subsystem level (experience, 1 years)
- Developing and maintaining design verification (DV) testbenches, test cases, and test environments (experience)
- Master's degree or PhD (degree in Electrical Engineering, Computer Engineering, or Computer Science with emphasis on computer architecture)
Responsibilities
- Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.
- Plan the verification of digital design blocks by understanding design specifications and collaborating with design engineers to identify key verification scenarios.
- Create and improve constrained-random verification environments using SystemVerilog and UVM. Optionally use SystemVerilog Assertions (SVA) and formal tools for formal verification.
- Perform power-aware simulations and formal verification to validate power management features like clock gating, power gating, and DVFS. Develop and implement power-aware test cases, including stress and corner-case scenarios, for power integrity.
- Develop and execute coverage-driven verification plans to ensure comprehensive coverage of ASIC designs. Collaborate with design engineers to resolve coverage issues and improve design quality.
Benefits
- Equal Opportunity: Google is proud to be an equal opportunity and affirmative action employer committed to building a representative workforce and providing equal employment opportunity regardless of protected characteristics.
- Culture: Creating a culture of belonging.
- Accommodations: Accommodations for applicants with needs by completing the Accommodations for Applicants form.
- Global Collaboration: English proficiency required for efficient global collaboration and communication.
Tags & Categories