Silicon IP RTL Design Senior Engineer, Google Cloud
Silicon IP RTL Design Senior Engineer, Google Cloud
Job Description
Google | Bengaluru, Karnataka, India. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability. In this role, you will be part of a team developing Application-specific integrated circuit (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with micro-architecture and solutions, and evaluate design options with performance and power. The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Locations
- Bengaluru, Karnataka, India
Salary
Estimated Salary Rangemedium confidence
80,000 - 150,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Digital Logic Design Principlesadvanced (Hardware Design)
- RTL Design Conceptsadvanced (Hardware Design)
- Verilogadvanced (Hardware Description Language)
- SystemVerilogadvanced (Hardware Description Language)
- Logic Synthesis Techniquesadvanced (Hardware Design)
- Low-Power Design Techniquesadvanced (Hardware Design)
- Pythonintermediate (Programming)
- Perlintermediate (Programming)
Required Qualifications
- Bachelor's Degree (degree in Electrical Engineering, Computer Engineering, Computer Science, or related field)
- Digital Logic Design, RTL Design, and Languages like Verilog or SystemVerilog (experience, 8 years)
- Logic Synthesis Techniques for RTL Optimization, Performance, Power, and Low-Power Design (experience, 8 years)
- System on a Chip (SoC) Designs and Integration Flows (experience)
- Arithmetic Units, Bus Architectures, Processor Design, Accelerators, or Memory Hierarchies (experience)
- High Performance and Low Power Design Techniques (experience)
Responsibilities
- Own microarchitecture and implementation of Internet Protocols (IPs) and subsystems.
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications.
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
- Identify and drive power, performance and area improvements for the domains owned.
Benefits
- Equal Opportunity: Google is proud to be an equal opportunity and affirmative action employer committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing equal employment opportunity.
- Accommodations: If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Tags & Categories
Silicon IP RTL Design Senior Engineer, Google Cloud
Silicon IP RTL Design Senior Engineer, Google Cloud
Job Description
Google | Bengaluru, Karnataka, India. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability. In this role, you will be part of a team developing Application-specific integrated circuit (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with micro-architecture and solutions, and evaluate design options with performance and power. The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Locations
- Bengaluru, Karnataka, India
Salary
Estimated Salary Rangemedium confidence
80,000 - 150,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Digital Logic Design Principlesadvanced (Hardware Design)
- RTL Design Conceptsadvanced (Hardware Design)
- Verilogadvanced (Hardware Description Language)
- SystemVerilogadvanced (Hardware Description Language)
- Logic Synthesis Techniquesadvanced (Hardware Design)
- Low-Power Design Techniquesadvanced (Hardware Design)
- Pythonintermediate (Programming)
- Perlintermediate (Programming)
Required Qualifications
- Bachelor's Degree (degree in Electrical Engineering, Computer Engineering, Computer Science, or related field)
- Digital Logic Design, RTL Design, and Languages like Verilog or SystemVerilog (experience, 8 years)
- Logic Synthesis Techniques for RTL Optimization, Performance, Power, and Low-Power Design (experience, 8 years)
- System on a Chip (SoC) Designs and Integration Flows (experience)
- Arithmetic Units, Bus Architectures, Processor Design, Accelerators, or Memory Hierarchies (experience)
- High Performance and Low Power Design Techniques (experience)
Responsibilities
- Own microarchitecture and implementation of Internet Protocols (IPs) and subsystems.
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications.
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
- Identify and drive power, performance and area improvements for the domains owned.
Benefits
- Equal Opportunity: Google is proud to be an equal opportunity and affirmative action employer committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing equal employment opportunity.
- Accommodations: If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Tags & Categories