Silicon Senior Physical Design Engineer, TPU, Google Cloud
Silicon Senior Physical Design Engineer, TPU, Google Cloud
Job Description
Google | Bengaluru, Karnataka, India. Minimum qualifications: Bachelor’s degree in Electrical Engineering or equivalent practical experience. 5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs. Experience with System on a Chip (SoC) cycles. Experience in high-performance, high-frequency, and low-power designs. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
Locations
- Bengaluru, Karnataka, India
Salary
Estimated Salary Rangemedium confidence
80,000 - 150,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- advanced designadvanced (VLSI)
- clock/voltage domain crossingadvanced (VLSI)
- Design for Testing (DFT)advanced (VLSI)
- low power designsadvanced (VLSI)
- System on a Chip (SoC) cyclesadvanced (VLSI)
- high-performance designsadvanced (VLSI)
- high-frequency designsadvanced (VLSI)
- System Verilogintermediate (Programming)
- TCL scriptingintermediate (Scripting)
- VLSI design in SoCadvanced (VLSI)
- ASIC designadvanced (VLSI)
- layout verificationadvanced (VLSI)
- design rulesadvanced (VLSI)
Required Qualifications
- Bachelor’s degree (degree in Electrical Engineering)
- advanced design experience (experience in VLSI, 5 years)
- SoC cycles experience (experience in VLSI, 5 years)
- high-performance, high-frequency, and low-power designs (experience in VLSI, 5 years)
- Master’s degree (degree in Electrical Engineering)
- coding with System Verilog and scripting with TCL (experience in Programming)
- VLSI design in SoC or multiple-cycles of SoC in ASIC design (experience in VLSI)
- layout verification and design rules (experience in VLSI)
Responsibilities
- Define and drive the implementation of physical design methodologies.
- Take ownership of one or more physical design partitions or top level.
- Manage timing and power consumption of the design.
- Contribute to design methodology, libraries, and code review.
- Define the physical design related rule sets for the functional design engineers.
Benefits
- equal opportunity: Google is proud to be an equal opportunity and affirmative action employer committed to building a workforce that is representative of the users we serve.
- culture: Creating a culture of belonging and providing equal employment opportunity.
- accommodations: If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Tags & Categories
Silicon Senior Physical Design Engineer, TPU, Google Cloud
Silicon Senior Physical Design Engineer, TPU, Google Cloud
Job Description
Google | Bengaluru, Karnataka, India. Minimum qualifications: Bachelor’s degree in Electrical Engineering or equivalent practical experience. 5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs. Experience with System on a Chip (SoC) cycles. Experience in high-performance, high-frequency, and low-power designs. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.
Locations
- Bengaluru, Karnataka, India
Salary
Estimated Salary Rangemedium confidence
80,000 - 150,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- advanced designadvanced (VLSI)
- clock/voltage domain crossingadvanced (VLSI)
- Design for Testing (DFT)advanced (VLSI)
- low power designsadvanced (VLSI)
- System on a Chip (SoC) cyclesadvanced (VLSI)
- high-performance designsadvanced (VLSI)
- high-frequency designsadvanced (VLSI)
- System Verilogintermediate (Programming)
- TCL scriptingintermediate (Scripting)
- VLSI design in SoCadvanced (VLSI)
- ASIC designadvanced (VLSI)
- layout verificationadvanced (VLSI)
- design rulesadvanced (VLSI)
Required Qualifications
- Bachelor’s degree (degree in Electrical Engineering)
- advanced design experience (experience in VLSI, 5 years)
- SoC cycles experience (experience in VLSI, 5 years)
- high-performance, high-frequency, and low-power designs (experience in VLSI, 5 years)
- Master’s degree (degree in Electrical Engineering)
- coding with System Verilog and scripting with TCL (experience in Programming)
- VLSI design in SoC or multiple-cycles of SoC in ASIC design (experience in VLSI)
- layout verification and design rules (experience in VLSI)
Responsibilities
- Define and drive the implementation of physical design methodologies.
- Take ownership of one or more physical design partitions or top level.
- Manage timing and power consumption of the design.
- Contribute to design methodology, libraries, and code review.
- Define the physical design related rule sets for the functional design engineers.
Benefits
- equal opportunity: Google is proud to be an equal opportunity and affirmative action employer committed to building a workforce that is representative of the users we serve.
- culture: Creating a culture of belonging and providing equal employment opportunity.
- accommodations: If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Tags & Categories