Junior ASIC/FPGA Verification & Validation Engineer
Honeywell
Junior ASIC/FPGA Verification & Validation Engineer
Job Description
Junior ASIC/FPGA Verification & Validation Engineer
Overview
Join Honeywell's innovative team in Brno as a Junior ASIC/FPGA Verification & Validation Engineer. You will contribute to cutting-edge projects spanning Urban Air Mobility, Military Mission Computers, and Space design. In this hybrid role (International location), you'll collaborate with multidisciplinary teams to ensure the reliability and performance of complex FPGA and ASIC designs. Honeywell, a Fortune 100 leader in aerospace and advanced technologies, offers a dynamic environment where your work impacts global missions. This position is ideal for early-career engineers passionate about hardware verification in high-stakes industries.
Key Responsibilities
- Develop and execute verification testbenches using SystemVerilog and UVM methodologies for ASIC/FPGA designs.
- Perform validation testing on hardware prototypes, including functional, performance, and stress tests.
- Debug and resolve verification failures, collaborating with design teams to implement fixes.
- Automate test scripts and regression suites using Python, Tcl, or similar tools.
- Document test plans, results, and coverage reports to meet aerospace and defense standards (e.g., DO-254, MIL-STD).
- Support integration of verified designs into larger systems for air, space, and military applications.
What Makes This Role Exciting
Be at the forefront of transformative technologies shaping the future of aviation and defense. Work on diverse, mission-critical projects with exposure to state-of-the-art tools and methodologies. Enjoy hybrid flexibility, mentorship from senior engineers, and opportunities for rapid career growth in a collaborative, global team. At Honeywell, your contributions drive real-world innovation while benefiting from a supportive culture focused on employee development and work-life balance.
Summary
As ASIC/FPGA Verification & Validation Engineer here at Honeywell in Brno, you will be part of a team working on new products that span from Urban Air Mobility through Military Mission Computer to Space design.
Locations
- Turanka 1387/100, , Brno, BM, CZ 62700
Salary
60,000 - 120,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- SystemVerilog and UVM verification methodologyintermediate
- Verilog/VHDL for RTL understandingintermediate
- Simulation and debugging tools (ModelSim, VCS, Vivado)intermediate
- Scripting for automation (Python, Tcl, Makefile)intermediate
- Strong problem-solving and analytical skillsintermediate
- Attention to detail and commitment to qualityintermediate
- Team collaboration and communication skillsintermediate
- Understanding of digital design principlesintermediate
- Experience with version control (Git)intermediate
- Basic knowledge of protocols (AXI, PCIe, Ethernet)intermediate
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (experience)
- 1-3 years of experience in ASIC/FPGA verification or validation (experience)
- Proficiency in HDLs such as Verilog or VHDL (experience)
- Hands-on experience with verification methodologies like UVM or OVM (experience)
- Familiarity with simulation tools (e.g., ModelSim, QuestaSim, Vivado) (experience)
- Basic knowledge of scripting languages (Python, Perl, or Tcl) (experience)
Preferred Qualifications
- Master's degree in Electrical Engineering or related field (experience)
- Experience with formal verification tools (e.g., JasperGold, OneSpin) (experience)
- Exposure to aerospace/defense standards (DO-254, MIL-STD-810) (experience)
Responsibilities
- Design, implement, and maintain UVM-based verification environments for FPGA/ASIC blocks
- Create and execute detailed test plans for pre-silicon verification and post-silicon validation
- Analyze coverage metrics (code, functional, toggle) and close gaps to achieve 100% coverage
- Collaborate with RTL designers to triage bugs and verify design fixes
- Develop automated regression test flows and CI/CD pipelines for efficient verification cycles
- Support hardware bring-up and validation on emulation platforms or lab equipment
- Contribute to design reviews and provide verification insights for improved design quality
Benefits
- general: Competitive salary and performance-based bonuses
- general: Comprehensive health, dental, and vision insurance
- general: Retirement savings plan with company matching
- general: Professional development programs and tuition reimbursement
- general: Flexible hybrid work model with work-life balance initiatives
- general: Employee stock purchase plan and wellness programs
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Answer 10 quick questions to check your fit for Junior ASIC/FPGA Verification & Validation Engineer @ Honeywell.
Related Books and Jobs
Junior ASIC/FPGA Verification & Validation Engineer
Honeywell
Junior ASIC/FPGA Verification & Validation Engineer
Job Description
Junior ASIC/FPGA Verification & Validation Engineer
Overview
Join Honeywell's innovative team in Brno as a Junior ASIC/FPGA Verification & Validation Engineer. You will contribute to cutting-edge projects spanning Urban Air Mobility, Military Mission Computers, and Space design. In this hybrid role (International location), you'll collaborate with multidisciplinary teams to ensure the reliability and performance of complex FPGA and ASIC designs. Honeywell, a Fortune 100 leader in aerospace and advanced technologies, offers a dynamic environment where your work impacts global missions. This position is ideal for early-career engineers passionate about hardware verification in high-stakes industries.
Key Responsibilities
- Develop and execute verification testbenches using SystemVerilog and UVM methodologies for ASIC/FPGA designs.
- Perform validation testing on hardware prototypes, including functional, performance, and stress tests.
- Debug and resolve verification failures, collaborating with design teams to implement fixes.
- Automate test scripts and regression suites using Python, Tcl, or similar tools.
- Document test plans, results, and coverage reports to meet aerospace and defense standards (e.g., DO-254, MIL-STD).
- Support integration of verified designs into larger systems for air, space, and military applications.
What Makes This Role Exciting
Be at the forefront of transformative technologies shaping the future of aviation and defense. Work on diverse, mission-critical projects with exposure to state-of-the-art tools and methodologies. Enjoy hybrid flexibility, mentorship from senior engineers, and opportunities for rapid career growth in a collaborative, global team. At Honeywell, your contributions drive real-world innovation while benefiting from a supportive culture focused on employee development and work-life balance.
Summary
As ASIC/FPGA Verification & Validation Engineer here at Honeywell in Brno, you will be part of a team working on new products that span from Urban Air Mobility through Military Mission Computer to Space design.
Locations
- Turanka 1387/100, , Brno, BM, CZ 62700
Salary
60,000 - 120,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- SystemVerilog and UVM verification methodologyintermediate
- Verilog/VHDL for RTL understandingintermediate
- Simulation and debugging tools (ModelSim, VCS, Vivado)intermediate
- Scripting for automation (Python, Tcl, Makefile)intermediate
- Strong problem-solving and analytical skillsintermediate
- Attention to detail and commitment to qualityintermediate
- Team collaboration and communication skillsintermediate
- Understanding of digital design principlesintermediate
- Experience with version control (Git)intermediate
- Basic knowledge of protocols (AXI, PCIe, Ethernet)intermediate
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (experience)
- 1-3 years of experience in ASIC/FPGA verification or validation (experience)
- Proficiency in HDLs such as Verilog or VHDL (experience)
- Hands-on experience with verification methodologies like UVM or OVM (experience)
- Familiarity with simulation tools (e.g., ModelSim, QuestaSim, Vivado) (experience)
- Basic knowledge of scripting languages (Python, Perl, or Tcl) (experience)
Preferred Qualifications
- Master's degree in Electrical Engineering or related field (experience)
- Experience with formal verification tools (e.g., JasperGold, OneSpin) (experience)
- Exposure to aerospace/defense standards (DO-254, MIL-STD-810) (experience)
Responsibilities
- Design, implement, and maintain UVM-based verification environments for FPGA/ASIC blocks
- Create and execute detailed test plans for pre-silicon verification and post-silicon validation
- Analyze coverage metrics (code, functional, toggle) and close gaps to achieve 100% coverage
- Collaborate with RTL designers to triage bugs and verify design fixes
- Develop automated regression test flows and CI/CD pipelines for efficient verification cycles
- Support hardware bring-up and validation on emulation platforms or lab equipment
- Contribute to design reviews and provide verification insights for improved design quality
Benefits
- general: Competitive salary and performance-based bonuses
- general: Comprehensive health, dental, and vision insurance
- general: Retirement savings plan with company matching
- general: Professional development programs and tuition reimbursement
- general: Flexible hybrid work model with work-life balance initiatives
- general: Employee stock purchase plan and wellness programs
Tags & Categories
Answer 10 quick questions to check your fit for Junior ASIC/FPGA Verification & Validation Engineer @ Honeywell.
Related Books and Jobs