Junior ASIC/FPGA Verification & Validation Engineer
Honeywell
Junior ASIC/FPGA Verification & Validation Engineer
Job Description
Junior ASIC/FPGA Verification & Validation Engineer
Overview
Join Honeywell's innovative team in Brno as a Junior ASIC/FPGA Verification & Validation Engineer. You will contribute to cutting-edge projects spanning Urban Air Mobility, Military Mission Computers, and Space design. This hybrid role offers the flexibility to work internationally while collaborating with world-class engineers on high-impact technologies that shape the future of aerospace and defense. At Honeywell, a Fortune 100 company, you'll gain hands-on experience in a dynamic environment fostering growth and innovation.
Key Responsibilities
- Develop and execute comprehensive verification testbenches using SystemVerilog and UVM methodologies for ASIC and FPGA designs.
- Perform validation testing on hardware prototypes, including lab bring-up, functional testing, and performance characterization.
- Debug complex RTL designs, identify root causes of failures, and collaborate on design fixes with cross-functional teams.
- Automate test flows using scripting languages like Python or Tcl to enhance efficiency and coverage.
- Contribute to design reviews, documentation, and continuous improvement of verification processes.
- Support integration of verified IP blocks into larger SoC systems for aerospace and defense applications.
What Makes This Role Exciting
Be part of groundbreaking projects that power next-generation Urban Air Mobility vehicles, rugged Military Mission Computers, and reliable Space systems. Work in a hybrid model with international exposure, mentorship from senior engineers, and access to Honeywell's state-of-the-art facilities. Thrive in a collaborative culture that values innovation, offers rapid career progression, and impacts global missions. If you're passionate about hardware verification and eager to launch your career at a leader in aerospace technology, this is your opportunity to excel.
Summary
As Junior ASIC/FPGA Verification & Validation Engineer here at Honeywell in Brno, you will be part of a team working on new products that span from Urban Air Mobility through Military Mission Computer to Space design.
Locations
- Turanka 1387/100, , Brno, BM, CZ 62700
Salary
60,000 - 120,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- SystemVerilog and UVM verification methodologyintermediate
- Verilog/VHDL RTL design and simulationintermediate
- FPGA tools (Vivado, Quartus) and ASIC flowsintermediate
- Debugging with oscilloscopes, logic analyzers, and protocol analyzersintermediate
- Python/Tcl/Perl scripting for automationintermediate
- Strong problem-solving and analytical skillsintermediate
- Attention to detail and commitment to qualityintermediate
- Effective communication and teamwork abilitiesintermediate
- Understanding of digital design principles and timing analysisintermediate
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (experience)
- 1-3 years of experience in ASIC/FPGA verification or validation (experience)
- Proficiency in HDLs such as Verilog or VHDL (experience)
- Hands-on experience with verification methodologies like UVM or OVM (experience)
- Familiarity with simulation tools (e.g., QuestaSim, VCS, Vivado) (experience)
- Basic knowledge of scripting languages (Python, Perl, or Tcl) (experience)
Preferred Qualifications
- Master's degree in Electrical Engineering or related field (experience)
- Experience with formal verification tools (e.g., JasperGold, OneSpin) (experience)
- Prior exposure to aerospace or defense projects (experience)
Responsibilities
- Design, implement, and maintain UVM-based verification environments for complex FPGA/ASIC designs
- Develop constrained-random test scenarios to achieve high functional coverage metrics
- Execute validation on FPGA emulation platforms and physical hardware prototypes
- Analyze simulation waveforms and hardware debug logs to resolve verification failures
- Collaborate with design and software teams to ensure seamless IP integration and system-level validation
- Document test plans, results, and methodologies for compliance with DO-254 and aerospace standards
- Optimize verification flows for performance, reusability, and scalability across projects
Benefits
- general: Competitive salary and performance-based bonuses
- general: Comprehensive health, dental, and vision insurance
- general: Retirement savings plan with company matching
- general: Professional development programs and tuition reimbursement
- general: Flexible hybrid work arrangements and work-life balance initiatives
- general: Employee stock purchase plan and wellness programs
Tags & Categories
Answer 10 quick questions to check your fit for Junior ASIC/FPGA Verification & Validation Engineer @ Honeywell.
Related Books and Jobs
Junior ASIC/FPGA Verification & Validation Engineer
Honeywell
Junior ASIC/FPGA Verification & Validation Engineer
Job Description
Junior ASIC/FPGA Verification & Validation Engineer
Overview
Join Honeywell's innovative team in Brno as a Junior ASIC/FPGA Verification & Validation Engineer. You will contribute to cutting-edge projects spanning Urban Air Mobility, Military Mission Computers, and Space design. This hybrid role offers the flexibility to work internationally while collaborating with world-class engineers on high-impact technologies that shape the future of aerospace and defense. At Honeywell, a Fortune 100 company, you'll gain hands-on experience in a dynamic environment fostering growth and innovation.
Key Responsibilities
- Develop and execute comprehensive verification testbenches using SystemVerilog and UVM methodologies for ASIC and FPGA designs.
- Perform validation testing on hardware prototypes, including lab bring-up, functional testing, and performance characterization.
- Debug complex RTL designs, identify root causes of failures, and collaborate on design fixes with cross-functional teams.
- Automate test flows using scripting languages like Python or Tcl to enhance efficiency and coverage.
- Contribute to design reviews, documentation, and continuous improvement of verification processes.
- Support integration of verified IP blocks into larger SoC systems for aerospace and defense applications.
What Makes This Role Exciting
Be part of groundbreaking projects that power next-generation Urban Air Mobility vehicles, rugged Military Mission Computers, and reliable Space systems. Work in a hybrid model with international exposure, mentorship from senior engineers, and access to Honeywell's state-of-the-art facilities. Thrive in a collaborative culture that values innovation, offers rapid career progression, and impacts global missions. If you're passionate about hardware verification and eager to launch your career at a leader in aerospace technology, this is your opportunity to excel.
Summary
As Junior ASIC/FPGA Verification & Validation Engineer here at Honeywell in Brno, you will be part of a team working on new products that span from Urban Air Mobility through Military Mission Computer to Space design.
Locations
- Turanka 1387/100, , Brno, BM, CZ 62700
Salary
60,000 - 120,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- SystemVerilog and UVM verification methodologyintermediate
- Verilog/VHDL RTL design and simulationintermediate
- FPGA tools (Vivado, Quartus) and ASIC flowsintermediate
- Debugging with oscilloscopes, logic analyzers, and protocol analyzersintermediate
- Python/Tcl/Perl scripting for automationintermediate
- Strong problem-solving and analytical skillsintermediate
- Attention to detail and commitment to qualityintermediate
- Effective communication and teamwork abilitiesintermediate
- Understanding of digital design principles and timing analysisintermediate
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (experience)
- 1-3 years of experience in ASIC/FPGA verification or validation (experience)
- Proficiency in HDLs such as Verilog or VHDL (experience)
- Hands-on experience with verification methodologies like UVM or OVM (experience)
- Familiarity with simulation tools (e.g., QuestaSim, VCS, Vivado) (experience)
- Basic knowledge of scripting languages (Python, Perl, or Tcl) (experience)
Preferred Qualifications
- Master's degree in Electrical Engineering or related field (experience)
- Experience with formal verification tools (e.g., JasperGold, OneSpin) (experience)
- Prior exposure to aerospace or defense projects (experience)
Responsibilities
- Design, implement, and maintain UVM-based verification environments for complex FPGA/ASIC designs
- Develop constrained-random test scenarios to achieve high functional coverage metrics
- Execute validation on FPGA emulation platforms and physical hardware prototypes
- Analyze simulation waveforms and hardware debug logs to resolve verification failures
- Collaborate with design and software teams to ensure seamless IP integration and system-level validation
- Document test plans, results, and methodologies for compliance with DO-254 and aerospace standards
- Optimize verification flows for performance, reusability, and scalability across projects
Benefits
- general: Competitive salary and performance-based bonuses
- general: Comprehensive health, dental, and vision insurance
- general: Retirement savings plan with company matching
- general: Professional development programs and tuition reimbursement
- general: Flexible hybrid work arrangements and work-life balance initiatives
- general: Employee stock purchase plan and wellness programs
Tags & Categories
Answer 10 quick questions to check your fit for Junior ASIC/FPGA Verification & Validation Engineer @ Honeywell.
Related Books and Jobs