Static Timing Methodology Development for Gate Level Timing Signoff
IBM
Static Timing Methodology Development for Gate Level Timing Signoff
Job Description
Static Timing Methodology Development for Gate Level Timing Signoff
📋 Job Overview
Join IBM's Einstimer Development team within the Electronic Design Automation organization to work on static timing analysis for high-performance hardware designs used in IBM's next generation systems. This role involves developing leading-edge algorithms and AI technology to enhance design team productivity and chip performance. Candidates will contribute to IBM's leadership in creating high-performing computers and innovative hardware solutions.
📍 Location: BANGALORE, IN (Remote/Hybrid)
💼 Career Level: Professional
🎯 Key Responsibilities
- Develop and enhance static timing analysis for high-performance hardware designs
- Lead development of leading-edge algorithms and AI technology within EDA solutions
- Increase design team productivity and chip quality and performance
- Coordinate deliverables and requirements from various areas within and outside the organization
- Provide input towards decisions affecting system development, logical and physical design, and methodology directions
✅ Required Qualifications
- BS, MS, or PhD degree in Computer Science, Computer Engineering, or Electronics & Communication Engineering
- Highly motivated and energetic individuals willing to go the extra mile
⭐ Preferred Qualifications
- Background in Machine Learning/AI and/or Data Science
🛠️ Required Skills
- Strong interpersonal skills
- Cadence tools
- Synopsys tools
- VLSI knowledge
- VHDL/Verilog
- Computer architecture
- Machine Learning/AI
🎁 Benefits & Perks
- Opportunities for learning and career development
- Encouragement to be courageous and experiment daily
- Continuous trust and support in a thriving environment
- Growth-minded culture with openness to feedback and learning
Locations
- BANGALORE, IN, India (Remote)
Salary
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Strong interpersonal skillsintermediate
- Cadence toolsintermediate
- Synopsys toolsintermediate
- VLSI knowledgeintermediate
- VHDL/Verilogintermediate
- Computer architectureintermediate
- Machine Learning/AIintermediate
Required Qualifications
- BS, MS, or PhD degree in Computer Science, Computer Engineering, or Electronics & Communication Engineering (experience)
- Highly motivated and energetic individuals willing to go the extra mile (experience)
Preferred Qualifications
- Background in Machine Learning/AI and/or Data Science (experience)
Responsibilities
- Develop and enhance static timing analysis for high-performance hardware designs
- Lead development of leading-edge algorithms and AI technology within EDA solutions
- Increase design team productivity and chip quality and performance
- Coordinate deliverables and requirements from various areas within and outside the organization
- Provide input towards decisions affecting system development, logical and physical design, and methodology directions
Benefits
- general: Opportunities for learning and career development
- general: Encouragement to be courageous and experiment daily
- general: Continuous trust and support in a thriving environment
- general: Growth-minded culture with openness to feedback and learning
Tags & Categories
Answer 10 quick questions to check your fit for Static Timing Methodology Development for Gate Level Timing Signoff @ IBM.
Related Books and Jobs
Static Timing Methodology Development for Gate Level Timing Signoff
IBM
Static Timing Methodology Development for Gate Level Timing Signoff
Job Description
Static Timing Methodology Development for Gate Level Timing Signoff
📋 Job Overview
Join IBM's Einstimer Development team within the Electronic Design Automation organization to work on static timing analysis for high-performance hardware designs used in IBM's next generation systems. This role involves developing leading-edge algorithms and AI technology to enhance design team productivity and chip performance. Candidates will contribute to IBM's leadership in creating high-performing computers and innovative hardware solutions.
📍 Location: BANGALORE, IN (Remote/Hybrid)
💼 Career Level: Professional
🎯 Key Responsibilities
- Develop and enhance static timing analysis for high-performance hardware designs
- Lead development of leading-edge algorithms and AI technology within EDA solutions
- Increase design team productivity and chip quality and performance
- Coordinate deliverables and requirements from various areas within and outside the organization
- Provide input towards decisions affecting system development, logical and physical design, and methodology directions
✅ Required Qualifications
- BS, MS, or PhD degree in Computer Science, Computer Engineering, or Electronics & Communication Engineering
- Highly motivated and energetic individuals willing to go the extra mile
⭐ Preferred Qualifications
- Background in Machine Learning/AI and/or Data Science
🛠️ Required Skills
- Strong interpersonal skills
- Cadence tools
- Synopsys tools
- VLSI knowledge
- VHDL/Verilog
- Computer architecture
- Machine Learning/AI
🎁 Benefits & Perks
- Opportunities for learning and career development
- Encouragement to be courageous and experiment daily
- Continuous trust and support in a thriving environment
- Growth-minded culture with openness to feedback and learning
Locations
- BANGALORE, IN, India (Remote)
Salary
2,500,000 - 4,200,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Strong interpersonal skillsintermediate
- Cadence toolsintermediate
- Synopsys toolsintermediate
- VLSI knowledgeintermediate
- VHDL/Verilogintermediate
- Computer architectureintermediate
- Machine Learning/AIintermediate
Required Qualifications
- BS, MS, or PhD degree in Computer Science, Computer Engineering, or Electronics & Communication Engineering (experience)
- Highly motivated and energetic individuals willing to go the extra mile (experience)
Preferred Qualifications
- Background in Machine Learning/AI and/or Data Science (experience)
Responsibilities
- Develop and enhance static timing analysis for high-performance hardware designs
- Lead development of leading-edge algorithms and AI technology within EDA solutions
- Increase design team productivity and chip quality and performance
- Coordinate deliverables and requirements from various areas within and outside the organization
- Provide input towards decisions affecting system development, logical and physical design, and methodology directions
Benefits
- general: Opportunities for learning and career development
- general: Encouragement to be courageous and experiment daily
- general: Continuous trust and support in a thriving environment
- general: Growth-minded culture with openness to feedback and learning
Tags & Categories
Answer 10 quick questions to check your fit for Static Timing Methodology Development for Gate Level Timing Signoff @ IBM.
Related Books and Jobs