Senior FPGA Engineer - Careers at Leidos
Leidos
Senior FPGA Engineer - Careers at Leidos
Job Description
Join Leidos Defense Sector as a Senior FPGA Engineer
Leidos Defense Sector Space Business Area seeks a Senior FPGA Engineer in San Diego, CA, to deliver cutting-edge solutions for national defense. Leverage your expertise in full-lifecycle FPGA development for space-qualified LEO/MEO/GEO designs, CBRN sensors, and high-tech missions supporting SDA, RCO, DARPA.
Primary Responsibilities
- Own complete FPGA lifecycle: architecture, HDL coding (VHDL/SystemVerilog), testing, hardware integration.
- Mentor juniors, conduct design reviews, author interface documents and technical reports.
- Develop DSP/image processing on Xilinx Zynq Ultrascale+, Versal SoCs; implement PCIe Gen4, 40GbE, DDR4.
- Build self-checking testbenches, achieve timing closure on Virtex/Kintex7, PolarFire, Versal.
- Troubleshoot hardware, analyze failures, execute test plans (0-10% travel).
Basic Qualifications
- BS EE/CE +12yrs or MS +10yrs experience; full FPGA ownership proven.
- Top Secret clearance eligibility; fluent in Vivado/ModelSim, high-speed Xilinx timing closure.
- Hands-on HDL, test equipment proficiency.
Preferred Skills
Space-qualified designs, digital signal processing, multi-disciplinary team collaboration. Thrive in fast-paced environments delivering 'can't fail' defense solutions.
Explore Leidos Defense: enterprise IT, intel systems, C2, cybersecurity. Make an impact—apply today!
Locations
- San Diego, California, United States
Salary
131,300 - 237,350 USD / yearly
131,300 - 237,350 USD / yearly
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- FPGA Architecture & Designintermediate
- VHDL/SystemVerilog HDLintermediate
- Vivado/ModelSim/Rivieraintermediate
- Timing Closure & Synthesisintermediate
- Xilinx Zynq Ultrascale+/Versalintermediate
- DSP & Image Processing Algorithmsintermediate
- PCIe Gen4, 40GbE Ethernet, DDR4intermediate
- Testbench Development & Verificationintermediate
- SERDES, PLLs, High-Speed Protocolsintermediate
- Electronics Test Equipmentintermediate
Required Qualifications
- Bachelor's +12 years or Master's +10 years in Electrical/Computer Engineering (experience)
- Proven full lifecycle FPGA design: architect, code, test, integrate (experience)
- Active eligibility for Top Secret Security Clearance (experience)
- Hands-on HDL design, simulation, synthesis for Xilinx FPGAs (Virtex/Kintex7, Versal) (experience)
- Experience with test equipment: oscilloscopes, logic analyzers, function generators (experience)
Responsibilities
- Architect, develop, code, test, and integrate high-density FPGA designs for space/CBRN sensors
- Mentor junior FPGA engineers and lead design reviews
- Develop/test FPGA designs for Xilinx Zynq Ultrascale+, Versal SoCs with DSP applications
- Implement HDL testbenches, ensure timing closure, and integrate IP (PCIe, Ethernet, DDR)
- Perform data analysis, root cause failure analysis, and execute test plans (0-10% travel)
Benefits
- general: Competitive salary $131K-$237K with performance incentives
- general: Comprehensive medical, dental, vision, and 401(k) matching
- general: Professional development and tuition reimbursement
- general: Flexible work options and paid time off
- general: Mission-driven impact on national defense and space programs
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Answer 10 quick questions to check your fit for Senior FPGA Engineer - Careers at Leidos @ Leidos.
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Senior FPGA Engineer - Careers at Leidos
Leidos
Senior FPGA Engineer - Careers at Leidos
Job Description
Join Leidos Defense Sector as a Senior FPGA Engineer
Leidos Defense Sector Space Business Area seeks a Senior FPGA Engineer in San Diego, CA, to deliver cutting-edge solutions for national defense. Leverage your expertise in full-lifecycle FPGA development for space-qualified LEO/MEO/GEO designs, CBRN sensors, and high-tech missions supporting SDA, RCO, DARPA.
Primary Responsibilities
- Own complete FPGA lifecycle: architecture, HDL coding (VHDL/SystemVerilog), testing, hardware integration.
- Mentor juniors, conduct design reviews, author interface documents and technical reports.
- Develop DSP/image processing on Xilinx Zynq Ultrascale+, Versal SoCs; implement PCIe Gen4, 40GbE, DDR4.
- Build self-checking testbenches, achieve timing closure on Virtex/Kintex7, PolarFire, Versal.
- Troubleshoot hardware, analyze failures, execute test plans (0-10% travel).
Basic Qualifications
- BS EE/CE +12yrs or MS +10yrs experience; full FPGA ownership proven.
- Top Secret clearance eligibility; fluent in Vivado/ModelSim, high-speed Xilinx timing closure.
- Hands-on HDL, test equipment proficiency.
Preferred Skills
Space-qualified designs, digital signal processing, multi-disciplinary team collaboration. Thrive in fast-paced environments delivering 'can't fail' defense solutions.
Explore Leidos Defense: enterprise IT, intel systems, C2, cybersecurity. Make an impact—apply today!
Locations
- San Diego, California, United States
Salary
131,300 - 237,350 USD / yearly
131,300 - 237,350 USD / yearly
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- FPGA Architecture & Designintermediate
- VHDL/SystemVerilog HDLintermediate
- Vivado/ModelSim/Rivieraintermediate
- Timing Closure & Synthesisintermediate
- Xilinx Zynq Ultrascale+/Versalintermediate
- DSP & Image Processing Algorithmsintermediate
- PCIe Gen4, 40GbE Ethernet, DDR4intermediate
- Testbench Development & Verificationintermediate
- SERDES, PLLs, High-Speed Protocolsintermediate
- Electronics Test Equipmentintermediate
Required Qualifications
- Bachelor's +12 years or Master's +10 years in Electrical/Computer Engineering (experience)
- Proven full lifecycle FPGA design: architect, code, test, integrate (experience)
- Active eligibility for Top Secret Security Clearance (experience)
- Hands-on HDL design, simulation, synthesis for Xilinx FPGAs (Virtex/Kintex7, Versal) (experience)
- Experience with test equipment: oscilloscopes, logic analyzers, function generators (experience)
Responsibilities
- Architect, develop, code, test, and integrate high-density FPGA designs for space/CBRN sensors
- Mentor junior FPGA engineers and lead design reviews
- Develop/test FPGA designs for Xilinx Zynq Ultrascale+, Versal SoCs with DSP applications
- Implement HDL testbenches, ensure timing closure, and integrate IP (PCIe, Ethernet, DDR)
- Perform data analysis, root cause failure analysis, and execute test plans (0-10% travel)
Benefits
- general: Competitive salary $131K-$237K with performance incentives
- general: Comprehensive medical, dental, vision, and 401(k) matching
- general: Professional development and tuition reimbursement
- general: Flexible work options and paid time off
- general: Mission-driven impact on national defense and space programs
Tags & Categories
Answer 10 quick questions to check your fit for Senior FPGA Engineer - Careers at Leidos @ Leidos.
Related Books and Jobs