ASIC Design Engineer
Meta
ASIC Design Engineer
Job Description
Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.
Locations
- Sunnyvale, CA, USA
Salary
Estimated Salary Rangemedium confidence
14,000,000 - 35,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Required Qualifications
- Requires a Bachelor's degree (or foreign degree equivalent) in Computer Science, Computer Engineering, or a related field and 3 years of experience in the job-offered or in a related occupation Requires 3 years of experience in the following: Verilog or System Verilog Micro-architecture and RTL development for complex control and data path IPs Experience in SoC Micro-architecture, Design and Integration Experience in CPU, NOC, Memory, Peripheral Subsystems or Video Codec designs Synthesis, Timing Closure or Formal Verification Methodology TCL, Python, Perl, or Shell-scripting Working with complex control and data path IPs (experience, 3 years)
Responsibilities
- Responsible for micro-architecture development. Perform RTL development using Verilog, System Verilog and/or HLS. Responsible for Lint, CDC, Synthesis, & Power Optimization. Collaborate with verification and emulation teams in test planning, development, and debugging. Collaborate with implementation team to close the design on timing and power.
Tags & Categories
ASIC Design Engineer
Meta
ASIC Design Engineer
Job Description
Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.
Locations
- Sunnyvale, CA, USA
Salary
Estimated Salary Rangemedium confidence
14,000,000 - 35,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Required Qualifications
- Requires a Bachelor's degree (or foreign degree equivalent) in Computer Science, Computer Engineering, or a related field and 3 years of experience in the job-offered or in a related occupation Requires 3 years of experience in the following: Verilog or System Verilog Micro-architecture and RTL development for complex control and data path IPs Experience in SoC Micro-architecture, Design and Integration Experience in CPU, NOC, Memory, Peripheral Subsystems or Video Codec designs Synthesis, Timing Closure or Formal Verification Methodology TCL, Python, Perl, or Shell-scripting Working with complex control and data path IPs (experience, 3 years)
Responsibilities
- Responsible for micro-architecture development. Perform RTL development using Verilog, System Verilog and/or HLS. Responsible for Lint, CDC, Synthesis, & Power Optimization. Collaborate with verification and emulation teams in test planning, development, and debugging. Collaborate with implementation team to close the design on timing and power.
Tags & Categories