ASIC Engineer, Architecture
Meta
ASIC Engineer, Architecture
Job Description
Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.
Locations
- Austin, TX, USA
Salary
Salary not disclosed
Estimated Salary Rangemedium confidence
15,000,000 - 35,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Required Qualifications
- Master’s degree (or foreign degree equivalent) in Electrical Engineering, Computer Science, Computer Software, Computer Engineering, Telecommunications and Network Engineering or related field and 4 years of work experience in job offered or in a computer-related occupation Requires 4 years of experience in the following: Object oriented design and C++ Hardware design and simulation SystemC modeling or TLM2 models Cycle-accurate SoC performance model environments Make file Creation and Python, Perl or PHP Working with hardware IP blocks, sub-units and systems and Knowledge of Computer Architecture principles such as hardware pipelining, memory hierarchy and network on chip interconnects (experience, 4 years)
Responsibilities
- Create modeling specification documents based on architecture and micro-architecture specifications. Implement transaction level models(TLM) as well as cycle accurate models of configurable hardware IP blocks, sub-units, systems and behavioral components, aimed at verifying the functional correctness and performance of the ASIC design. Collaborate with the kernel development team to qualify the performance of these microbenchmarks on the System C/C++models. Collaborate with the Design Verification team to debug and analyze functional and performance discrepancies between System C/C++models and RTL implementation. Create and maintain Make files and Python programs. Leverage knowledge of hardware design and simulation to assist with video transcode and machine learning ASIC design.
Tags & Categories
ASIC Engineer, Architecture
Meta
ASIC Engineer, Architecture
Job Description
Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.
Locations
- Austin, TX, USA
Salary
Salary not disclosed
Estimated Salary Rangemedium confidence
15,000,000 - 35,000,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Required Qualifications
- Master’s degree (or foreign degree equivalent) in Electrical Engineering, Computer Science, Computer Software, Computer Engineering, Telecommunications and Network Engineering or related field and 4 years of work experience in job offered or in a computer-related occupation Requires 4 years of experience in the following: Object oriented design and C++ Hardware design and simulation SystemC modeling or TLM2 models Cycle-accurate SoC performance model environments Make file Creation and Python, Perl or PHP Working with hardware IP blocks, sub-units and systems and Knowledge of Computer Architecture principles such as hardware pipelining, memory hierarchy and network on chip interconnects (experience, 4 years)
Responsibilities
- Create modeling specification documents based on architecture and micro-architecture specifications. Implement transaction level models(TLM) as well as cycle accurate models of configurable hardware IP blocks, sub-units, systems and behavioral components, aimed at verifying the functional correctness and performance of the ASIC design. Collaborate with the kernel development team to qualify the performance of these microbenchmarks on the System C/C++models. Collaborate with the Design Verification team to debug and analyze functional and performance discrepancies between System C/C++models and RTL implementation. Create and maintain Make files and Python programs. Leverage knowledge of hardware design and simulation to assist with video transcode and machine learning ASIC design.
Tags & Categories