ASIC Verification Engineer, PCIe
Meta
ASIC Verification Engineer, PCIe
Job Description
Meta is hiring Application-Specific Integrated Circuit (ASIC) Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.
As a Design Verification Engineer, you will be part of a team working with the best in the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
Locations
- Bangalore, India
Salary
Estimated Salary Rangehigh confidence
25,000,000 - 55,000,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- PCIe specifications, protocols, and standardsintermediate (Hardware)
- Verilogintermediate (Programming)
- SystemVerilogintermediate (Programming)
- UVMintermediate (Verification)
- C/C++intermediate (Programming)
- Pythonintermediate (Programming)
- Scripting (Python, Perl, TCL)intermediate (Programming)
Required Qualifications
- Bachelor's degree (degree in Computer Science, Computer Engineering, relevant technical field)
- Relevant experience (experience, 8 years)
- ASIC development (experience)
- PCIe verification (Transaction, Link, Physical layer) (experience)
- IP, Cluster and SoC level verification (RTL and Gate Level) (experience)
- DV setup for complex Subsystem and ASICs (experience)
Preferred Qualifications
- PCIe Gen6/Gen7 DV testbench development (experience, 12 years)
- PCIe vendor VIP integration (experience)
- Performance verification of PCIe Sub-System for AI/ML (experience)
- Automated flows and scripts for data exploration and analysis (experience)
- Revision control systems (Mercurial, Git, SVN) (experience)
- Simulators and waveform debugging tools (experience)
Responsibilities
- Develop and execute verification plans, test cases, and scripts to ensure PCIe interface functionality, performance, and compliance with industry standards
- Collaborate with design teams to understand the PCIe interface architecture and identify potential issues
- Create and maintain testbenches, including simulation models and tests
- Perform simulation-based testing, including functional, performance, and compliance testing
- Analyze test results, identify defects, and work with design teams to resolve issues
- Stay up-to-date with industry trends, standards, and best practices related to PCIe verification
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Mentor engineers to drive and deliver high confidence verification for highly complex ASIC projects
Tags & Categories
ASIC Verification Engineer, PCIe
Meta
ASIC Verification Engineer, PCIe
Job Description
Meta is hiring Application-Specific Integrated Circuit (ASIC) Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.
As a Design Verification Engineer, you will be part of a team working with the best in the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
Locations
- Bangalore, India
Salary
Estimated Salary Rangehigh confidence
25,000,000 - 55,000,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- PCIe specifications, protocols, and standardsintermediate (Hardware)
- Verilogintermediate (Programming)
- SystemVerilogintermediate (Programming)
- UVMintermediate (Verification)
- C/C++intermediate (Programming)
- Pythonintermediate (Programming)
- Scripting (Python, Perl, TCL)intermediate (Programming)
Required Qualifications
- Bachelor's degree (degree in Computer Science, Computer Engineering, relevant technical field)
- Relevant experience (experience, 8 years)
- ASIC development (experience)
- PCIe verification (Transaction, Link, Physical layer) (experience)
- IP, Cluster and SoC level verification (RTL and Gate Level) (experience)
- DV setup for complex Subsystem and ASICs (experience)
Preferred Qualifications
- PCIe Gen6/Gen7 DV testbench development (experience, 12 years)
- PCIe vendor VIP integration (experience)
- Performance verification of PCIe Sub-System for AI/ML (experience)
- Automated flows and scripts for data exploration and analysis (experience)
- Revision control systems (Mercurial, Git, SVN) (experience)
- Simulators and waveform debugging tools (experience)
Responsibilities
- Develop and execute verification plans, test cases, and scripts to ensure PCIe interface functionality, performance, and compliance with industry standards
- Collaborate with design teams to understand the PCIe interface architecture and identify potential issues
- Create and maintain testbenches, including simulation models and tests
- Perform simulation-based testing, including functional, performance, and compliance testing
- Analyze test results, identify defects, and work with design teams to resolve issues
- Stay up-to-date with industry trends, standards, and best practices related to PCIe verification
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Mentor engineers to drive and deliver high confidence verification for highly complex ASIC projects
Tags & Categories