As an integral part of our cross-discipline engineering team in Mission Systems that encompasses Digital Verification Engineering to support ASIC and FPGA product development. Work closely with design and verification engineers and will utilize your knowledge of modern verification methods, tools and techniques. Perform functional verification of register transfer level (RTL) code of a complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilogl. Development of testbench, tests, verification IP (VIP), verification models, coverage models, extensive simulation and debug, code coverage and functional coverage, generation and analysis of reports and metrics, documentation etc. Ability to operate in a team environment and collaborate across the different teams as required to accomplish the goals. Bachelor's degree with 5 years of experience, a Master's degree with 3 years of experience or a PhD with 0 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree. U.S Citizenship is required. Experience developing testplans, participating in reviews, test development and RTL debug Bachelor's degree with 8 years of experience, a Master's degree with 6 years of experience or a PhD with 3 years of experience in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree. U.S Citizenship is required The ability to obtain/maintain an Active DoD secret clearance and Special Program Access (SAP). 3 years of experience with FPGA or ASIC verification using UVM Experience developing testplans, participating in reviews, test development and RTL debug Advanced Degree with at least 3+ years of professional experience in related industry Experience with data structures, object oriented programming languages and concepts Experience with Verification IP integration and/or development Experience with a coverage-driven verification methodology from planning through closure Knowledge of industry standard bus or I/O interfaces Experience with SystemVerilog Assertions (SVA) FPGA/ASIC design and/or development process experience Experience with scripting languages (Bash, Perl, Python, Tcl, Makefile) Knowledge of digital signal processing