Responsible for DFT (Design for Testabilty) aspects of ASIC Design thorough understanding of digital design concepts Responsible with ASIC development process. Knowledgeable in VHDL, Verilog or SystemVerilog RTL coding and be highly proficient in DFT methodologies. Responsible for operating in a team environment and collaborate across the different teams as required to accomplish the goals. Bachelor's degree with 5 years of experience, a Master's degree with 3 years of experience or a Ph.D. with 1 years of experience in Science, Technology, Engineering, Mathematics, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree. Ability to obtain/maintain a clearance once hired Experience in full product life cycle of ASIC Design Experience with Cadence and/or Mentor test insertion and ATPG tools Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTA Experience generating test patterns and analyzing and debugging test failures Experience working with test engineers to implement ATPG vectors on tester hardware Proficiency in HDL (VHDL/Verilog/SystemVerilog) and scripting languages such as Tcl, Python or Perl Effective communication and presentation skills and high proficiency in technical problem solving Master's Degree in Electrical or Computer Engineering Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus Active Clearance or higher Bachelor's degree with 8 years of experience, a Master's degree with 6 years of experience or a Ph.D. with 4 years of experience in Science, Technology, Engineering, Mathematics, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree. Ability to obtain/maintain a security clearance once hired Experience in full product life cycle of ASIC Design Experience with Cadence and/or Mentor test insertion and ATPG tools Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTA Experience with memory BIST and logic BIST Experience generating test patterns and analyzing and debugging test failures Experience working with test engineers to implement ATPG vectors on tester hardware Master's Degree in Electrical or Computer Engineering Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus Active Clearance or higher