Responsible for static timing analysis on digital designs to ensure timing requirements are met Identify timing violations and perform or propose changes to fix them Work closely with design, verification, design-for-test and physical design teams to optimize the timing and improve design performance Develop and validate timing constraints and ensure they are correctly implemented Develop and maintain timing methodologies and flows for efficient timing analysis and closure Conduct design reviews to provide recommendations for meeting timing goals. Troubleshoot timing issues and provide effective solutions. Stay up-to-date with industry trends and advancements in static timing analysis tools and methodologies. Bachelor's degree with 8 years of experience, a Master's degree with 6 years of experience or a Ph.D. with 4 years of experience in Science, Technology, Engineering, Mathematics, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree. Ability to obtain/maintain an active Secret clearance and a Special Program Access (SAP) prior to start Master's Degree in Electrical or Computer Engineering Knowledge of Synthesis, Place & Route (P&R), and Design-for-Test (DFT) methodologies Active DoD Secret Clearance or higher Effective communication and presentation skills and high proficiency in technical problem solving