As a Digital Verification Lead Engineer, you will have an opportunity to be a part of a technology development organization that is collaborative, open, transparent, team-oriented, and flexible, where continuous learning is encouraged, all within a culture of design. We are seeking an exceptional Senior Functional Verification Engineer specializing in ASIC and FPGA technologies. The ideal candidate will play a critical role in behavioral simulation, and comprehensive functional verification processes. The Debug and Staff Lead Design Verification Engineer will be responsible leading the verification team for debug, emulation, and test development for state-of-the-art Digital Logic (High Speed Serial). Other responsibilities will include:

Design Entry & RTL Development:

Create comprehensive test-benches for behavioral simulation Design and implement verification strategies for complex digital systems Ensure RTL implementation meets precise design specification requirements Conduct in-depth behavioral simulations across ASIC and FPGA Generate and execute advanced UVM Test cases Achieve 95% code coverage goals and functional coverage across critical metrics Perform detailed code coverage analysis, including: (Statement coverage, Expression coverage, Branch coverage, Toggle coverage) Develop comprehensive Universal Verification Methodology (UVM) simulation environments Work closely with design teams to validate RTL implementations Provide detailed feedback and recommendations for design improvements Participate in design reviews and Lead in verification planning Contribute to continuous improvement of verification methodologies Bachelor's degree in Computer Engineering, BSEE, or comparable STEM Degree and 12 years industry experience in a design verification role or Master's Degree plus 10 years experience or PhD plus 7 years experience Experience with functional verification methodology for the full life cycle of products with leading a team with various levels of experience and skills Demonstrated experience leading Verification Teams Specialized experience in functional verification with multiple Tape Outs Expert-level proficiency in Hardware Description Languages: (Verilog, VHDL, SystemVerilog) Extensive knowledge of: (comprehensive RTL design methodologies, Behavioral simulation techniques, Code coverage strategies) Extensive experience with industry-standard EDA tools (Cadence, Synopsys, Mentor Graphics) Extensive experience with verification methodologies:

Universal Verification Methodology (UVM) Regression and automation framework development This position requires the applicant to be a U.S. citizen Candidates must be willing to obtain and maintain a security clearance. Advanced Degrees in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields Experience with advanced Gate Level Simulations Experience with the management of schedule, cost, metric reporting, and trade studies