NVIDIA builds the world's largest chips. As the chip size grows larger and larger, power efficiency become more and more important, whether the chip is used in datacenter, in cars, or in PCs. We design a PMU IP starting from 15y ago to help making the chip always working in the best efficient way for both idle scenarios and active scenarios. The PMU IP is composed by a RISC-V core and various of custom designed control logics. The HW logic collects the status from the entire chip, processing the data, and co-work with SW running on the RISC-V core to determine the best operation point. As the PMU design becomes more and more complicated and used in more and more chips, we are hiring a ASIC Design Verification Engineer to help building a more powerful PMU.What you'll be doing:Study IP/system-level architect to define unitlevel testbench structure.IP level verification for various features defined for GPU PMU and THERM IP.Fullchip verification for GPU PMU IP and Tegra THERM IP.What we need to see:Master School students new colleague graduate who are major in Electronic science and technology.Self-driving, active thinking and problem solving.Solid ASIC design background.Familiar with Verilog, perl (or python) script. Familiar with C/C++.NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!