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ASIC Floorplan Design Engineer - New College Grad 2025

NVIDIA

Engineering Jobs

ASIC Floorplan Design Engineer - New College Grad 2025

full-timePosted: Oct 22, 2025

Job Description

We are now looking for a ASIC Floorplan Design Engineer - NCG.NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.What you will be doing:Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunitiesSolve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.You will build tools and improve existing infrastructure to optimize chip area and speed of execution.What we need to see:Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.Experience in Verilog, System Verilog or similar HVLExperience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.Python, Perl and C/C++ programming language experienceWays to stand out from the crowd:Experience in driving development of large scale ASIC floorplan is a huge plus.NVIDIA is widely considered to be one of the technology world’s most desirable employers. Our products are leading the way with groundbreaking developments in Artificial Intelligence, Autonomous Driving, High-Performance Computing and Visualization. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 96,000 USD - 161,000 USD for Level 1, and 108,000 USD - 184,000 USD for Level 2.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until October 26, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Locations

  • Santa Clara, CA, US

Salary

Estimated Salary Rangemedium confidence

12,000,000 - 18,000,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • ASIC Floorplan Designintermediate
  • SoC Designintermediate
  • GPU Designintermediate
  • VLSIintermediate
  • Computer Architectureintermediate
  • Verilogintermediate
  • SystemVerilogintermediate
  • HVLintermediate
  • CADintermediate
  • Physical Design Methodologiesintermediate
  • Chip Floorplanintermediate
  • Power Distributionintermediate
  • Clock Distributionintermediate
  • Packagingintermediate
  • Place and Route (P&R)intermediate
  • Timing Closureintermediate
  • Pythonintermediate
  • Perlintermediate
  • C/C++intermediate
  • Tool Developmentintermediate
  • Infrastructure Improvementintermediate
  • Area Optimizationintermediate
  • Timing Analysisintermediate
  • Routing Congestion Resolutionintermediate
  • Communication Skillsintermediate
  • Interpersonal Skillsintermediate
  • Teamworkintermediate

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ASIC Floorplan Design Engineer - New College Grad 2025

NVIDIA

Engineering Jobs

ASIC Floorplan Design Engineer - New College Grad 2025

full-timePosted: Oct 22, 2025

Job Description

We are now looking for a ASIC Floorplan Design Engineer - NCG.NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.What you will be doing:Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunitiesSolve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.You will build tools and improve existing infrastructure to optimize chip area and speed of execution.What we need to see:Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.Experience in Verilog, System Verilog or similar HVLExperience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.Python, Perl and C/C++ programming language experienceWays to stand out from the crowd:Experience in driving development of large scale ASIC floorplan is a huge plus.NVIDIA is widely considered to be one of the technology world’s most desirable employers. Our products are leading the way with groundbreaking developments in Artificial Intelligence, Autonomous Driving, High-Performance Computing and Visualization. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 96,000 USD - 161,000 USD for Level 1, and 108,000 USD - 184,000 USD for Level 2.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until October 26, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Locations

  • Santa Clara, CA, US

Salary

Estimated Salary Rangemedium confidence

12,000,000 - 18,000,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • ASIC Floorplan Designintermediate
  • SoC Designintermediate
  • GPU Designintermediate
  • VLSIintermediate
  • Computer Architectureintermediate
  • Verilogintermediate
  • SystemVerilogintermediate
  • HVLintermediate
  • CADintermediate
  • Physical Design Methodologiesintermediate
  • Chip Floorplanintermediate
  • Power Distributionintermediate
  • Clock Distributionintermediate
  • Packagingintermediate
  • Place and Route (P&R)intermediate
  • Timing Closureintermediate
  • Pythonintermediate
  • Perlintermediate
  • C/C++intermediate
  • Tool Developmentintermediate
  • Infrastructure Improvementintermediate
  • Area Optimizationintermediate
  • Timing Analysisintermediate
  • Routing Congestion Resolutionintermediate
  • Communication Skillsintermediate
  • Interpersonal Skillsintermediate
  • Teamworkintermediate

Target Your Resume for "ASIC Floorplan Design Engineer - New College Grad 2025" , NVIDIA

Get personalized recommendations to optimize your resume specifically for ASIC Floorplan Design Engineer - New College Grad 2025. Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "ASIC Floorplan Design Engineer - New College Grad 2025" , NVIDIA

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Tags & Categories

United States of America

Answer 10 quick questions to check your fit for ASIC Floorplan Design Engineer - New College Grad 2025 @ NVIDIA.

Quiz Challenge
10 Questions
~2 Minutes
Instant Score

Related Books and Jobs

No related jobs found at the moment.