Resume and JobRESUME AND JOB
NVIDIA logo

ASIC Physical Design Engineer (RDSS Intern)

NVIDIA

Engineering Jobs

ASIC Physical Design Engineer (RDSS Intern)

full-timePosted: Oct 2, 2025

Job Description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. With the continuous improvement of chip technology, design scale and performance/power ratio, the physical design of digital chips is facing outstanding challenges in high frequency, low power consumption and multiple applications. High efficiency, high quality of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of process and related methodology work. You will face the biggest challenge based on the most advanced process on building chips in the world. What you'll be doing:Chip integration and netlist generationSynthesisRTL/netlist quality checkFormal VerificationConstraints creation and validation, timing budget.Work with ASIC team to analyze/resolve special timing issues.Cross-Team collaboration to implement chip partitioning and floorplanWork in conjunction with PR engineers to achieve timing closure for both partition and full chip levelAchieve special mode timing closure, such as io, test, clock, async etc.Function eco creationDevelop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout)Flow automation development for above areasMethodology in any of above areas. What we need to see:MS in EE or MicroelectronicsProject experience in IC design implementationCourses taken in circuit design, digital designHand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is helpfulProficient user of Python or TCL is helpfulProficient in English reading and writing With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

Locations

  • Hsinchu, Taiwan

Salary

Estimated Salary Rangemedium confidence

600,000 - 1,200,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • ASIC Physical Designintermediate
  • RTL Designintermediate
  • Synthesisintermediate
  • Formal Verificationintermediate
  • Constraints Definitionintermediate
  • Timing Closureintermediate
  • Sign Offintermediate
  • Chip Integrationintermediate
  • Netlist Generationintermediate
  • RTL/Netlist Quality Checkintermediate
  • Timing Budgetintermediate
  • Timing Analysisintermediate
  • ECO Creationintermediate
  • Chip Partitioningintermediate
  • Floorplanningintermediate
  • Timing Closure Flowintermediate
  • Process Methodologyintermediate
  • Cross-Team Collaborationintermediate
  • Visionintermediate
  • Innovationintermediate

Target Your Resume for "ASIC Physical Design Engineer (RDSS Intern)" , NVIDIA

Get personalized recommendations to optimize your resume specifically for ASIC Physical Design Engineer (RDSS Intern). Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "ASIC Physical Design Engineer (RDSS Intern)" , NVIDIA

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Tags & Categories

Taiwan

Answer 10 quick questions to check your fit for ASIC Physical Design Engineer (RDSS Intern) @ NVIDIA.

Quiz Challenge
10 Questions
~2 Minutes
Instant Score

Related Books and Jobs

No related jobs found at the moment.

NVIDIA logo

ASIC Physical Design Engineer (RDSS Intern)

NVIDIA

Engineering Jobs

ASIC Physical Design Engineer (RDSS Intern)

full-timePosted: Oct 2, 2025

Job Description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. With the continuous improvement of chip technology, design scale and performance/power ratio, the physical design of digital chips is facing outstanding challenges in high frequency, low power consumption and multiple applications. High efficiency, high quality of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of process and related methodology work. You will face the biggest challenge based on the most advanced process on building chips in the world. What you'll be doing:Chip integration and netlist generationSynthesisRTL/netlist quality checkFormal VerificationConstraints creation and validation, timing budget.Work with ASIC team to analyze/resolve special timing issues.Cross-Team collaboration to implement chip partitioning and floorplanWork in conjunction with PR engineers to achieve timing closure for both partition and full chip levelAchieve special mode timing closure, such as io, test, clock, async etc.Function eco creationDevelop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout)Flow automation development for above areasMethodology in any of above areas. What we need to see:MS in EE or MicroelectronicsProject experience in IC design implementationCourses taken in circuit design, digital designHand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is helpfulProficient user of Python or TCL is helpfulProficient in English reading and writing With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

Locations

  • Hsinchu, Taiwan

Salary

Estimated Salary Rangemedium confidence

600,000 - 1,200,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • ASIC Physical Designintermediate
  • RTL Designintermediate
  • Synthesisintermediate
  • Formal Verificationintermediate
  • Constraints Definitionintermediate
  • Timing Closureintermediate
  • Sign Offintermediate
  • Chip Integrationintermediate
  • Netlist Generationintermediate
  • RTL/Netlist Quality Checkintermediate
  • Timing Budgetintermediate
  • Timing Analysisintermediate
  • ECO Creationintermediate
  • Chip Partitioningintermediate
  • Floorplanningintermediate
  • Timing Closure Flowintermediate
  • Process Methodologyintermediate
  • Cross-Team Collaborationintermediate
  • Visionintermediate
  • Innovationintermediate

Target Your Resume for "ASIC Physical Design Engineer (RDSS Intern)" , NVIDIA

Get personalized recommendations to optimize your resume specifically for ASIC Physical Design Engineer (RDSS Intern). Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "ASIC Physical Design Engineer (RDSS Intern)" , NVIDIA

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Tags & Categories

Taiwan

Answer 10 quick questions to check your fit for ASIC Physical Design Engineer (RDSS Intern) @ NVIDIA.

Quiz Challenge
10 Questions
~2 Minutes
Instant Score

Related Books and Jobs

No related jobs found at the moment.