We are now looking for a Power Optimization Engineer – New College Grad! NVIDIA prides in having energy efficient products. We believe in continuing to maintain our products' energy efficiency compared to competition is key to our continued success. Our team is privileged to work on Power Optimization of Data center, gaming and automotive GPU chips. We also work on power optimization of Networking chips. The gamut of GPUs and networking chips requires the team to provide architecture, micro-architecture, RTL Design, methodology and AI based power optimization solutions. You will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for NVIDIA's next generation GPUs and Networking products. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements. What You'll Be Doing:Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.Use Artificial intelligence to devliver RTL and/or Architecture Power optimization solutions.Develop and share best practices for performing pre-silicon power analysis.Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.Select and run a wide variety of workloads for power analysis.Prototype a new architectural feature in Verilog and analyze power. What We Need To See:Pursuing BS or MS in Electrical Engineering, Computer Engineering, or related fields with coursework or experience in AI.Strong understanding of concepts of energy consumption, estimation, data movement and low power design.Strong coding/automation skills, preferably in Python, Perl, and C++.Strong analytical skills with go-getter attitude.Familiarity with Verilog and ASIC design principles, including knowledge of Power Artist, PTPX (Prime Power RTL, RTL Architect). Previous internships and/or work on Power Optimization would be beneficial.NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 108,000 USD - 184,000 USD for Level 2, and 136,000 USD - 212,750 USD for Level 3.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until November 3, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.