NVIDIA is seeking a highly motivated Senior Design Verification Engineer to play a critical role in verifying next-generation NVLink High-Speed I/O (HSIO) controllers for industry-leading GPUs. This is a unique opportunity to contribute to cutting-edge products spanning consumer graphics, self-driving vehicles, and artificial intelligence—all within a collaborative, technology-driven environment. At NVIDIA, we’re redefining the future of computing. From revolutionizing gaming and cinematic visual effects to powering breakthroughs in AI, robotics, and autonomous driving, our GPUs have evolved from graphics engines into platforms that simulate human intelligence. Join us in shaping the next era of AI computing.What You'll Be Doing:Drive the verification of ASIC design and architecture for NVLink HSIO controllers at the IP and sub-system levels using industry-standard methodologies like UVM.Develop reusable testbenches, including bus functional models (BFMs), monitors, checkers, and scoreboards following coverage-driven verification practices.Define verification strategy by analyzing design specifications, creating detailed test plans, and building the infrastructure required to ensure design correctness.Work closely with architects, RTL designers, and pre- and post-silicon teams to drive end-to-end verification and silicon readiness.Debug functional failures and optimize verification flows to improve productivity and coverage.What We Need to See:Bachelors or Masters Degree (or equivalent experience) with 8+ years of relevant experienceStrong background in Verilog/SystemVerilog, and familiarity with unit, subsystem, or SoC-level verification.Expertise in UVM-based random-constrained testing, functional coverage, and assertion-based verification.Proficiency with simulation tools (e.g., VCS, Questa, Xcelium).Excellent debugging and problem-solving skills.Effective communication skills and the ability to work collaboratively across cross-functional teams.Ways to Stand Out From the Crowd:Proven experience verifying interconnect or I/O protocols such as PCIE, CXL, USB, or SATA.Strong understanding of system-level HSIO architecture and integration challenges.Proficiency in scripting languages such as Python, Perl, or other automation tools used in DV environments.Experience contributing to test automation infrastructure or CI/CD systems for hardware verification is a plus.NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world at NVIDIA. Are you a creative and autonomous engineer who loves a challenge? Join our HSIO Verification team and help us build future interconnect architectures that will continue to drive us forward in the fields of High Performance Computing, Graphics and AI.#LI-HybridYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until September 19, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.